AD9736BBCRL(RevB) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9736BBCRL Datasheet PDF : 72 Pages
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Data Sheet
AD9734/AD9735/AD9736
DACCLK
DATACLK_OUT
DATACLK_IN
DATA_IN
A
DSS1
D1
DSS2
INTERNAL DELAY
EXTERNAL DELAY
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
QR
SAMPLE_HOLD
SAMPLE_SETUP
SAMPLE_DELAY
A
C
E
G
I
K
M
O
Q
D2
B
D
F
H
J
L
N
P
WRITE_PTR1
M0
M1
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
SAFE ZONE
ERROR ZONE
A
I
B
J
M2
M3
DATA 'A' CAN BE
SAFELY READ FROM
THE FIFO IN THE
M4
SAFE ZONE. IN THE
ERROR ZONE, THE
POINTERS MAY
M5
BRIEFLY OVERLAP
DUE TO CLOCK JITTER
OR NOISE.
M6
C
D
E
F
G
FIFOSTAT IS SET
EQUAL TO THE
WRITE POINTER
EACH TIME THE
READ POINTER
CHANGES FROM
7 TO 0.
M7
H
READ_PTR1
FIFOSTAT
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
4
4
4
DAC_DATA
A
B
C
D
E
F
G
H
I
J
K
LM
Figure 83. Sync Logic Timing Diagram
Rev. B | Page 43 of 72
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