ADP3193AJCPZ-RL View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADP3193AJCPZ-RL Datasheet PDF : 32 Pages
| |||
ADP3193A
COUT SELECTION
The required output decoupling for the regulator is typically
recommended by Intel for various processors and platforms.
Use some simple design guidelines to determine the require-
ments. These guidelines are based on having both bulk
capacitors and ceramic capacitors in the system.
First, select the total amount of ceramic capacitance. This is
based on the number and type of capacitor to be used. The best
location for ceramic capacitors is inside the socket, with twelve
to eighteen 1206-size pieces being the physical limit. Other
capacitors can be placed along the outer edge of the socket as well.
To determine the minimum amount of ceramic capacitance
required, start with a worst-case load step that occurs immediately
after a switching cycle has stopped. The ceramic capacitance then
delivers the charge to the load while the load is ramping up until
the VR responds with the next switching cycle.
Equation 15 provides the designer with a rough approximation
for determining the minimum ceramic capacitance. Due to the
complexity of the PCB parasitics and bulk capacitors, the actual
amount of ceramic capacitance required can vary.
C Z(MIN )
≥
1
2RO
⎡
×⎢
⎣
1
f SW
×
⎜⎝⎛
1
n
− D ⎟⎠⎞ −
ΔI O
2SR
⎤
⎥
⎦
(15)
The typical ceramic capacitors consist of multiple 10 μF or
22 μF capacitors. For this example, Equation 15 yields 265 μF,
so twenty-six 10 μF ceramic capacitors suffice.
Next, there is an upper limit imposed on the total amount of bulk
capacitance (CX), considering the VID on-the-fly voltage stepping
of the output (voltage step, VV, in time, tV, with error of VERR).
A lower limit is based on meeting the capacitance for load
release at a given maximum load step (ΔIO) and a maximum
allowable overshoot. The total amount of load release voltage
is ΔVO = ΔIO × RO + ΔVrl, where ΔVrl is the maximum allowable
overshoot voltage.
⎜⎛
⎟⎞
CX(MIN )
≥
⎜
⎜
⎜
⎜
⎝
n
×
⎜⎜⎝⎛
RO
L × Δ IO
+
ΔVrl
ΔIO
⎟⎟⎠⎞
×
VVID
− CZ
⎟
⎟
⎟
⎟
⎠
(16)
C X (MAX )
≤
L
nk 2 RO2
× VV
VVID
×
⎜⎛
⎜⎜⎝
1+ ⎜⎜⎝⎛tV
VVID
VV
×
nKRO
L
⎟⎟⎠⎞2
−
⎟⎞
1⎟⎟⎠
−CZ
(17)
where
k
=
−
ln
⎜⎜⎝⎛
VERR
VV
⎟⎟⎠⎞ .
To meet the conditions of these equations and transient response,
the ESR of the bulk capacitor bank (RX) should be less than two
times the droop resistance (RO). If CX(MIN) is larger than CX(MAX),
the system cannot meet the VID on-the-fly specification and
to maintain the output ripple may require the use of a smaller
inductor or more phases (in addition to increasing the switching
frequency).
This example uses twenty-six 10 μF 1206 MLC capacitors
(CZ = 260 μF). The VID on-the-fly step change is 450 mV in
230 μs with a settling error of 2.5 mV. The maximum allowable
load release overshoot for this example is 50 mV; therefore,
solving for the bulk capacitance yields
⎜⎛
⎟⎞
C
X(
MIN
)
≤
⎜
⎜
⎜
⎜⎜⎝
3
×
⎜⎜⎝⎛1.0
320 nH × 50 A
mΩ +
50 mV
50 A
⎟⎞
⎟⎠
×
1.4
V
−
260
⎟
μF ⎟
⎟
⎟⎟⎠
=
1.64
mF
320 nH × 450 mV
( ) CX(MAX) ≤ 3 × 5.22 × 1.0 mΩ 2 ×1.4 V ×
⎜⎛
⎜
⎜⎝
1+ ⎜⎜⎝⎛
230 μs ×1.4 V × 3 × 5.2 ×1.0
450 mV × 320 nH
mΩ
⎟⎞2
⎟⎠
⎟⎞
−1⎟ − 260 μF
⎟⎠
=
42.7
mF
where k = 5.2.
Using eight 560 μF aluminum-poly capacitors with a typical
ESR of 6 mΩ each yields CX = 4.48 mF with an RX = 0.75 mΩ.
One last check should be made to ensure that the ESL of the
bulk capacitors (LX) is low enough to limit the high frequency
ringing during a load change.
This is tested using
LX ≤ CZ × RO2× Q2
( ) LX ≤ 260 μF
×
1 mΩ 2 ×
4 = 347 pH
3
(18)
where Q2 is limited to 4/3 to ensure a critically damped system.
In this example, LX is approximately 240 pH for the eight
aluminum-poly capacitors, which satisfies this limitation. If the
LX of the chosen bulk capacitor bank is too large, the number of
ceramic capacitors needs to be increased, or lower ESL bulks
need to be used if there is excessive undershoot during a load
transient.
For this multimode control technique, all ceramic designs can
be used if the conditions of Equation 15 through Equation 18
are satisfied.
Rev. 0 | Page 22 of 32
Share Link: 