ADSP-BF516KSWZ-3(RevD) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-BF516KSWZ-3
(Rev.:RevD)

Blackfin Embedded Processor

Analog Devices 

ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16

Timer Cycle Timing

Table 41 and Figure 30 describe timer expired operations. The

input signal is asynchronous in “width capture mode” and

“external clock mode” and has an absolute maximum input fre-

quency of (fSCLK/2) MHz.

Table 41. Timer Cycle Timing

VDDEXT

1.8V Nominal

VDDEXT

2.5 V/3.3V Nominal

Parameter

Min

Max

Min

Max

Unit

Timing Characteristics

tWL1

Timer Pulse Width Input Low (Measured In SCLK Cycles) tSCLK

tSCLK

ns

tWH1

Timer Pulse Width Input High (Measured In SCLK Cycles) tSCLK

tSCLK

ns

tTIS2

Timer Input Setup Time Before CLKOUT Low

10

7

ns

tTIH2

Timer Input Hold Time After CLKOUT Low

–2

–2

ns

Switching Characteristics

tHTO

Timer Pulse Width Output (Measured In SCLK Cycles)

tSCLK – 1.5

(232–1)tSCLK tSCLK – 1

(232–1)tSCLK ns

tTOD

Timer Output Update Delay After CLKOUT High

6

6

ns

1 The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PF15 or PPI_CLK signals in PWM output mode.

2 Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.

CLKOUT

TMRx OUTPUT

TMRx INPUT

tTOD

tTIS

tTIH

tHTO

tWH,tWL

Figure 30. Timer Cycle Timing

Rev. D | Page 46 of 68 | April 2014

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