M48T248Y, M48T248V
Figure 7. Memory WRITE Cycle 1
ADDRESSES
tWC
tAW
CE
WE
DQ0–DQ7
tWR
tWP
tODW
tOEW
HIGH IMPEDANCE
tDS
tDH
DATA IN
STABLE
AI04231
Note: 1. OE = VIH or VIL. If OE = VIH during a WRITE cycle, the output buffers remain in a high impedance state.
2. If the CE low transition occurs simultaneously with or later than the WE low transition in WRITE Cycle 1, the output buffers remain
in a high impedance state during this period.
3. If the CE high transition occurs simultaneously with the WE high transition, the output buffers remain in a high impedance state
during this period.
10/24