NXP Semiconductors
P89LPC9301/931A1
8-bit microcontroller with accelerated two-clock 80C51 core
10. Dynamic characteristics
Table 12. Dynamic characteristics (12 MHz)
VDD = 2.4 V to 3.6 V unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.[1][2]
Symbol Parameter
Conditions
Variable clock
Min
Max
fosc(RC)
internal RC oscillator
frequency
nominal f = 7.3728 MHz
trimmed to ± 1 % at
Tamb = 25 °C; clock
doubler option = OFF
(default)
7.189
7.557
fosc(WD)
internal watchdog
oscillator frequency
nominal f = 14.7456 MHz;
clock doubler option = ON,
VDD = 2.7 V to 3.6 V
Tamb = 25 °C
14.378
380
15.114
420
fosc
Tcy(clk)
fCLKLP
oscillator frequency
clock cycle time
low-power select clock
frequency
see Figure 32
0
12
83
-
0
8
Glitch filter
tgr
glitch rejection time
P1.5/RST pin
-
50
any pin except P1.5/RST
-
15
tsa
signal acceptance time P1.5/RST pin
125
-
any pin except P1.5/RST
50
-
External clock
tCHCX
clock HIGH time
tCLCX
clock LOW time
tCLCH
clock rise time
tCHCL
clock fall time
Shift register (UART mode 0)
see Figure 32
see Figure 32
see Figure 32
see Figure 32
33
Tcy(clk) − tCLCX
33
Tcy(clk) − tCHCX
-
8
-
8
TXLXL
serial port clock cycle
time
see Figure 31
16Tcy(clk)
-
tQVXH
output data set-up to
clock rising edge time
see Figure 31
13Tcy(clk)
-
tXHQX
output data hold after
clock rising edge time
see Figure 31
-
Tcy(clk) + 20
tXHDX
input data hold after
clock rising edge time
see Figure 31
-
0
tXHDV
input data valid to clock see Figure 31
rising edge time
150
-
SPI interface
fSPI
SPI operating frequency
slave
master
0
CCLK⁄6
-
CCLK⁄4
fosc = 12 MHz Unit
Min Max
7.189 7.557 MHz
14.378 15.114 MHz
380 420 kHz
-
- MHz
-
- ns
-
- MHz
-
50 ns
-
15 ns
125
- ns
50
- ns
33
- ns
33
- ns
-
8 ns
-
8 ns
1333
- ns
1083
- ns
-
103 ns
-
0 ns
150
- ns
0
2.0 MHz
-
3.0 MHz
P89LPC9301_931A1_1
Preliminary data sheet
Rev. 01 — 9 April 2009
© NXP B.V. 2009. All rights reserved.
52 of 65