P89LPC9301(2009) View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
P89LPC9301
(Rev.:2009)
(Rev.:2009)
NXP Semiconductors.
P89LPC9301 Datasheet PDF : 65 Pages
| |||
NXP Semiconductors
P89LPC9301/931A1
8-bit microcontroller with accelerated two-clock 80C51 core
Table 13. Dynamic characteristics (18 MHz)
VDD = 3.0 V to 3.6 V unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.[1][2]
Symbol Parameter
Conditions
Variable clock
Min
Max
fosc(RC) internal RC oscillator
frequency
nominal f = 7.3728 MHz
trimmed to ± 1 % at
Tamb = 25 °C; clock
doubler option = OFF
(default)
7.189
7.557
nominal f = 14.7456 MHz;
clock doubler option = ON
14.378
15.114
fosc(WD) internal watchdog
oscillator frequency
Tamb = 25 °C
380
420
fosc
Tcy(clk)
fCLKLP
oscillator frequency
clock cycle time
low-power select clock
frequency
see Figure 32
0
18
55
-
0
8
Glitch filter
tgr
glitch rejection time
P1.5/RST pin
-
50
any pin except P1.5/RST
-
15
tsa
signal acceptance time P1.5/RST pin
125
-
any pin except P1.5/RST
50
-
External clock
tCHCX clock HIGH time
tCLCX clock LOW time
tCLCH clock rise time
tCHCL clock fall time
Shift register (UART mode 0)
see Figure 32
see Figure 32
see Figure 32
see Figure 32
22
Tcy(clk) − tCLCX
22
Tcy(clk) − tCHCX
-
5
-
5
TXLXL
serial port clock cycle
time
see Figure 31
16Tcy(clk)
-
tQVXH
output data set-up to
clock rising edge time
see Figure 31
13Tcy(clk)
-
tXHQX
output data hold after
clock rising edge time
see Figure 31
-
Tcy(clk) + 20
tXHDX
input data hold after
clock rising edge time
see Figure 31
-
0
tXHDV
input data valid to clock see Figure 31
rising edge time
150
-
SPI interface
fSPI
TSPICYC
SPI operating frequency
slave
master
SPI cycle time
see Figure 33, 34, 35, 36
slave
master
0
-
6⁄CCLK
4⁄CCLK
CCLK⁄6
CCLK⁄4
-
-
fosc = 18 MHz Unit
Min Max
7.189 7.557 MHz
14.378 15.114 MHz
380 420 kHz
-
- MHz
-
- ns
-
- MHz
-
50 ns
-
15 ns
125
- ns
50
- ns
22
- ns
22
- ns
-
5 ns
-
5 ns
888
- ns
722
- ns
-
75 ns
-
0 ns
150
- ns
0
3.0 MHz
-
4.5 MHz
333
- ns
222
- ns
P89LPC9301_931A1_1
Preliminary data sheet
Rev. 01 — 9 April 2009
© NXP B.V. 2009. All rights reserved.
54 of 65
Share Link: 