NXP Semiconductors
P89LPC9301/931A1
8-bit microcontroller with accelerated two-clock 80C51 core
SS
SPICLK
(CPOL = 0)
(input)
SPICLK
(CPOL = 1)
(input)
tSPIA
MISO
(output)
tSPIR
tSPILEAD
TSPICYC
tSPIF
tSPICLKH
tSPICLKL
tSPIR
tSPIF
tSPICLKL
tSPIR
tSPICLKH
tSPIOH
tSPIDV
not defined
tSPIOH
tSPIDV
slave MSB/LSB out
tSPIOH
tSPIDV
tSPILAG
tSPIR
slave LSB/MSB out
tSPIDIS
MOSI
(input)
tSPIDSU tSPIDH
MSB/LSB in
Fig 36. SPI slave timing (CPHA = 1)
tSPIDSU
tSPIDSU tSPIDH
LSB/MSB in
002aaa911
10.2 ISP entry mode
Table 14. Dynamic characteristics, ISP entry mode
VDD = 2.4 V to 3.6 V, unless otherwise specified.
Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
tVR
VDD active to RST active delay time pin RST
tRH
RST HIGH time
pin RST
tRL
RST LOW time
pin RST
50
-
-
1
-
32
1
-
-
Unit
µs
µs
µs
VDD
RST
tVR
tRH
tRL
Fig 37. ISP entry waveform
002aaa912
P89LPC9301_931A1_1
Preliminary data sheet
Rev. 01 — 9 April 2009
© NXP B.V. 2009. All rights reserved.
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