SAF-C505C-2RM View Datasheet(PDF) - Infineon Technologies

Part Name

Description

Manufacturer

SAF-C505C-2RM

8-bit Single-Chip Microcontroller

Infineon Technologies 

C505 / C505C

C505A / C505CA

The following Table 11 contains the functional description of all C505A-4E/C505CA-4E pins which

are required for OTP memory programming.

Table 11

Pin Definitions and Functions in Programming Mode

Symbol

RESET

PMSEL0

PMSEL1

Pin Number I/O

*)

4

I

5

I

7

I

Function

Reset

This input must be at static “1“ (active) level during the whole

programming mode.

Programming mode selection pins

These pins are used to select the different access modes in

programming mode. PMSEL1,0 must satisfy a setup time to the

rising edge of PALE. When the logic level of PMSEL1,0 is

changed, PALE must be at low level.

PMSEL1

0

0

1

1

PMSEL0

0

1

0

1

Access Mode

Reserved

Read version bytes

Program/read lock bits

Program/read OTP memory byte

PSEL

8

PRD

9

PALE

10

XTAL2 14

XTAL1 15

VSS

16

VDD

17

*) I = Input

O = Output

I

Basic programming mode select

This input is used for the basic programming mode selection

and must be switched according figure 3-1.

I

Programming mode read strobe

This input is used for read access control for OTP memory read,

Version Register read, and lock bit read operations.

I

Programming address latch enable

PALE is used to latch the high address lines. The high address

lines must satisfy a setup and hold time to/from the falling edge

of PALE. PALE must be at low level when the logic level of

PMSEL1,0 is changed.

O XTAL2

Output of the inverting oscillator amplifier.

I

XTAL1

Input to the oscillator amplifier.

– Circuit ground potential

must be applied in programming mode.

– Power supply terminal

must be applied in programming mode.

Data Sheet

52

08.00

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