PIC16F1513T-I/SS View Datasheet(PDF) - Microchip Technology
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Description
Manufacturer
PIC16F1513T-I/SS Datasheet PDF : 360 Pages
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PIC16(L)F1512/3
20.2.6 SPI OPERATION IN SLEEP MODE
In SPI Master mode, module clocks may be operating
at a different speed than when in Full-Power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the MSSP
clock is much faster than the system clock.
In Slave mode, when MSSP interrupts are enabled,
after the master completes sending data, an MSSP
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSP
interrupts should be disabled.
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the device
wakes. After the device returns to Run mode, the
module will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all eight bits have been received, the
MSSP interrupt flag bit will be set and if enabled, will
wake the device.
TABLE 20-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSELA
—
—
ANSA5
—
ANSA3
ANSA2 ANSA1 ANSA0
ANSELC
ANSC7
ANSC6
ANSC5 ANSC4
ANSC3
ANSC2
—
—
APFCON
—
—
—
—
—
—
SSSEL CCP2SEL
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
PIE1
TMR1GIE ADIE
RCIE
TXIE
SSPIE
CCP1IE TMR2IE TMR1IE
PIR1
TMR1GIF ADIF
RCIF
TXIF
SSPIF
CCP1IF TMR2IF TMR1IF
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
SSPCON1 WCOL
SSPOV SSPEN
CKP
SSPM<3:0>
SSPCON3 ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
TRISA
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
* Page provides register information.
104
111
101
69
70
72
179*
224
226
224
103
110
2012-2014 Microchip Technology Inc.
DS40001624C-page 185
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