PIC18LF45J10T-I/SP View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC18LF45J10T-I/SP
Microchip Technology
PIC18LF45J10T-I/SP Datasheet PDF : 358 Pages
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PIC18F45J10 FAMILY
FIGURE 23-13:
SSx
EXAMPLE SPI™ SLAVE MODE TIMING (CKE = 1)
82
70
SCKx
(CKP = 0)
83
71
72
SCKx
(CKP = 1)
80
SDOx
MSb
bit 6 - - - - - - 1
LSb
SDIx
75, 76
77
MSb In
bit 6 - - - - 1
LSb In
74
Note: Refer to Figure 23-3 for load conditions.
TABLE 23-17: EXAMPLE SPI™ SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70 TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑ Input
TSSL2SCL
TCY
—
71 TSCH
71A
SCKx Input High Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
72 TSCL
72A
SCKx Input Low Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
73A TB2B
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 —
74 TSCH2DIL, Hold Time of SDIx Data Input to SCKx Edge
TSCL2DIL
100
—
75 TDOR
SDOx Data Output Rise Time
—
25
76 TDOF
SDOx Data Output Fall Time
—
25
77 TSSH2DOZ SSx ↑ to SDOx Output High-Impedance
10
50
78 TSCR
SCKx Output Rise Time (Master mode)
—
25
79 TSCF
SCKx Output Fall Time (Master mode)
—
25
80 TSCH2DOV, SDOx Data Output Valid after SCKx Edge
TSCL2DOV
—
50
82 TSSL2DOV SDOx Data Output Valid after SSx ↓ Edge
—
50
83 TSCH2SSH, SSx ↑ after SCKx Edge
TSCL2SSH
1.5 TCY + 40 —
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns (Note 2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS39682C-page 320
Preliminary
© 2007 Microchip Technology Inc.
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