ST62P32BQ3 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST62P32BQ3

8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, 16-BIT AUTO-RELOAD TIMER, EEPROM, SPI AND UART

STMicroelectronics 

ST62T32B ST62E32B

4.5.4 DATA RECEPTION

The UART continuously looks for a falling edge on

the input pin whenever a transmission is not ac-

tive. Once an edge is detected it waits 1 bit time (8

states) to accommodate the Start bit, and then as-

sembles the following serial data stream into the

data register. The data in the ninth bit position is

copied into Bit 9, replacing any previous value set

for transmission. After all 9 bits have been re-

ceived, the Receiver waits for the duration of one

bit (for the Stop bit) and then transfers the received

data into the buffer register, allowing a following

character to be received. The interrupt flag

RXRDY is set to 1 as the data is transferred to the

buffer register and, if enabled, will generate an in-

terrupt.

If a transmission is started during the course of a

reception, the transmission takes priority and the

reception is stopped to free the resources for the

transmission. This implies that a handshaking sys-

tem must be implemented, as polling of the UART

to detect reception is not available.

Figure 38. UART Data Output

UAR TOE

4.5.5 INTERRUPT CAPABILITIES

Both reception and transmission processes can in-

duce interrupt to the core as defined in the inter-

rupt section. These interrupts are enabled by set-

ting TXIEN and RXIEN bit in the UARTCR register,

and TXMT and RXRDY flags are set accordingly

to the interrupt source.

4.5.6 REGISTERS

UART Data Register (UARTDR)

Address: D6h, Read/Write

7

0

D7 D6 D5 D4 D3

D2

D1

D0

Bit7-Bit0. UART data bits. A write to this register

loads the data into the transmit shift register and

triggers the start of transmission. In addition this

resets the transmit interrupt flag TXMT. A read of

this register returns the data from the Receive

buffer.

Warning. No Read/Write Instructions may be

used with this register as both transmit and receive

share the same address

T XD

PORT DATA

OUT PUT

1

MUX

0

TXD 1

VR02011

Table 20. Baud Rate Selection

BR2

BR2

BR0

0

0

0

0

0

1

0

1

0

0

1

1

1

0

0

1

0

1

1

1

0

1

1

1

fINT Division

6.656

3.328

1.664

832

416

256

208

Baud Rate

fINT = 8MHz

1200

fINT = 4MHz

600

2400

1200

4800

2400

9600

4800

19200

9600

31200

15600

38400

19200

Reserved

61/86

165

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