ST92E163N4D0 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST92E163N4D0
STMicroelectronics
ST92E163N4D0 Datasheet PDF : 224 Pages
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ST92163 - ELECTRICAL CHARACTERISTICS
EXTERNAL BUS TIMING TABLE
(VDD = 3.0 - 5.5V (1), TA = 0°C + 70°C, CLoad = 50pF, fINTCLK = 24MHz, unless otherwise specified)
N°
Symbol
Parameter
Value (Note)
Unit
Formula
Min Max
1 TsA (AS)
2 ThAS (A)
Address Set-up Time before AS ↑
Address Hold Time after AS ↑
Tck x Wa+TckH-9
TckL-4
12
ns
17
ns
3 TdAS (DR)
AS ↑ to Data Available (read)
Tck x (Wd+1)+3
45 ns
4 TwAS
AS Low Pulse Width
Tck x Wa+TckH-5
16
ns
5 TdAz (DS)
Address Float to DS ↓
0
0
ns
6 TwDS
DS Low Pulse Width
Tck x Wd+TckH-5
16
ns
7 TdDSR (DR)
8 ThDR (DS)
DS ↓ to Data Valid Delay (read)
Data to DS ↑ Hold Time (read)
Tck x Wd+TckH+4
7
25 ns
7
ns
9 TdDS (A)
DS ↑ to Address Active Delay
TckL+11
32
ns
10 TdDS (AS)
DS ↑ to AS ↓ Delay
TckL-4
17
ns
11 TsR/W (AS)
RW Set-up Time before ASN ↑
Tck x Wa+TckH-17
4
ns
12 TdDSR (R/W)
13 TdDW (DSW)
DS ↑ to RW and Address Not Valid Delay
Write Data Valid to DS ↓ Delay
TckL-1
-16
20
ns
-16
ns
14 TsD(DSW)
Write Data Set-up before DS ↑
Tck x Wd+TckH-16
5
ns
15 ThDS (DW)
Data Hold Time after DS ↑ (write)
TckL-3
18
ns
16 TdA (DR)
Address Valid to Data Valid Delay (read)
Tck x (Wa+Wd+1)+TckH-7
55 ns
17 TdAs (DS)
AS ↑ to DS ↓ Delay
TckL-6
15
ns
Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period,
prescaler value and number of wait cycles inserted.
The values in the right hand two columns show the timing minimum and maximum for an external clock at 24MHz, prescaler value of zero
and zero wait states.
(1) 3.0 - 4.0V voltage range is only available on devices with suffix L or V, with different frequency limitatio ns (L: 8 MHz, V: 16 MHz)
Legend:
Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2;
2 x OSCIN period when OSCIN is divided by 2;
OSCIN period x PLL factor when the PLL is enabled.
TckH = INTCLK high pulse width (normally = Tck/2, except when INTCLK = OSCIN, in which case it is OSCIN high pulse width)
TckL = INTCLK low pulse width (normally = Tck/2, except when INTCLK = OSCIN, in which case it is OSCIN low pulse width)
P = clock prescaling value (=PRS; division factor = 1+P)
Wa = wait cycles on AS; = max (P, programmed wait cycles in EMR2, requested wait cycles with WAIT)
Wd = wait cycles on DS; = max (P, programmed wait cycles in WCR, requested wait cycles with WAIT)
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