STA321
Clock management
Table 17.
IDF[3]
1
1
Input division factor (IDF) (continued)
IDF[2]
IDF[1]
IDF[0]
1
1
0
14
1
1
1
15
Input division factor (IDF)
Table 18. Loop division factor (LDF)
NDIV[5] NDIV[4] NDIV[3] NDIV[2] NDIV[1] NDIV[0]
Loop division factor (LDF)
0
0
0
0
x
x
NA
0
0
0
1
0
0
NA
0
0
0
1
0
1
5 (1)
0
0
0
1
1
0
6 (see note 3)
0
0
0
1
1
1
7 (see note 3)
0
0
1
0
0
0
8
…
…
…
…
…
…
…
1
1
0
1
1
0
54
1
1
0
1
1
1
55
1
1
1
x
x
x
NA
1. The LDF values of 5, 6 and 7 cannot be used when fractional synthesis mode is ON (PLL_FR_CTRL = 1)
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