Z8018033FSG View Datasheet(PDF) - Zilog

Part Name

Description

Manufacturer

Z8018033FSG

Microprocessor Unit

Zilog 

Z80180

Microprocessor Unit

54

Free Running Counter I/O Address = 18H

Mnemonic FRC: 18H

If data is written into the free running counter, the interval of DRAM refresh cycle and baud

rates for the ASCI and CSI/O are not guaranteed. In IOSTOP mode, the free running counter

continues counting down. It is initialized to FFH, during RESET.

Timer Data Register

76 54 32 1 0

Counting Data

Figure 47. Timer Data Register

DMA Source Address Register Channel 0

(SAR0: I/O ADDRESS = 20h to 22h) specifies the physical source address for channel 0

transfers. The register contains 20 bits and can specify up to 1024 KB memory addresses or

up to 64 KB I/O addresses. Channel 0 source can be memory, I/O, or memory mapped I/O.

For I/O, the most significant bits of this register identify the REQUEST HANDSHAKE

signal.

DMA Source Address Register, Channel 0L

Mnemonic SAR0L: Address 20h

Timer Data Register

76 54 32 1 0

—— —— — — — —

DMA Channel 0 Address

Figure 48. DMA Channel 0L

PS014004-1106

Architecture

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