Table 48-35.
Symbol
SPISPCK
SPI0
SPI1
SPI2
SPI3
SPI4
SPI5
SPI6
SPI7
SPI8
SPI9
SPI10
SPI11
SPI12
SPI13
SPI14
SPI15
SPI16
SPI Timings with 1.8V Peripheral Supply
Parameter
SPI Clock
MISO Setup time before SPCK rises
MISO Hold time after SPCK rises
SPCK rising to MOSI
MISO Setup time before SPCK falls
MISO Hold time after SPCK falls
SPCK falling to MOSI
SPCK falling to MISO
MOSI Setup time before SPCK rises
MOSI Hold time after SPCK rises
SPCK rising to MISO
MOSI Setup time before SPCK falls
MOSI Hold time after SPCK falls
NPCS0 setup to SPCK rising
NPCS0 hold after SPCK falling
NPCS0 setup to SPCK falling
NPCS0 hold after SPCK rising
NPCS0 falling to MISO valid
Figure 48-12. Min and Max Access Time for SPI Output Signal
Conditions
Master Mode
Slave Mode
SPCK
MISO
MOSI
SPI2max
SPI2min
SPI0
SPI1
Min
Max
Unit
–
66
MHz
18.0
–
ns
0
–
ns
0
0.2
ns
17.6
–
ns
0
–
ns
0
0.7
ns
6.0
18.9
ns
0.7
–
ns
1.7
–
ns
5.5
18.7
ns
0.5
–
ns
1.4
–
ns
17.4
–
ns
15.5
–
ns
17.8
–
ns
15.3
–
ns
5.4
17.7
ns
SAM9G46 Series [DATASHEET]
Atmel-11028G-ATARM-SAM9G46-Datasheet_08-Dec-15
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