AT91SAM9G46B-CU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
AT91SAM9G46B-CU Datasheet PDF : 1277 Pages
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52.1.3 Ethernet MAC 10/100 (EMAC)
52.1.3.1 EMAC: Setup Timing Violation in RMII Mode
A setup timing violation occurs when using the EMAC in RMII mode only with I/Os in a 1.8V range [1.65V:1.95V]
and when the line load exceeds 20 pF. The RMII mode is fully functional with I/Os in a 3.3V range [3.0V:3.6V].
Problem Fix/Workaround
None
52.1.4 Pulse Width Modulation Controller (PWM)
52.1.4.1 PWM: Zero Period
It is impossible to update a period equal to 0 by using the PWM_CUPD register.
Problem Fix/Workaround
None
52.1.5 RSTC: Software Reset During DDRAM Accesses
52.1.5.1 Software reset during DDRAM access
When a software reset (CPU and peripherals) occurs during DDRAM read access, the CPU will stop the DDRAM
clock.
The DDRAM maintains the data on the bus until the clock restarts. This will create a bus conflict if another
memory, sharing the external bus with the DDRAM, is accessed prior to completion of the read access to the
DDRAM. Such a conflict will occur when the device boots out of an external NAND or NOR Flash following a
software reset.
Problem Fix/Workaround
1) Boot from serial Flash
2) Before generating the software reset, the user must ensure that all the accesses to DDRAM are completed and
then put the DDRAM in self-refresh mode. The routine to generate the software reset must be located in internal
SRAM or in the ARM cache memory.
52.1.6 Static Memory Controller (SMC)
52.1.6.1 SMC: SMC Delay Access
In this document, the access is “Read/Write” in the Register Mapping table (SMC_DELAY1 to SMC_DELAY8
rows), and in the SMC DELAY I/O Register.
The current access is “Write-only”.
Problem Fix/Workaround
None
52.1.7 Serial Synchronous Controller (SSC)
52.1.7.1 SSC: Data sent without any frame synchro
When SSC is configured with the following conditions:
RF is in input,
TD is synchronized on a receive START (any condition: START field = 2 to 7)
TF toggles at each start of data transfer
Transmit STTDLY = 0
Check TD and TF after a receive START
The data is sent but there is not any toggle of the TF line.
1248 SAM9G46 Series [DATASHEET]
Atmel-11028G-ATARM-SAM9G46-Datasheet_08-Dec-15
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