AT91SAM9G46B-CU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
Manufacturer
AT91SAM9G46B-CU Datasheet PDF : 1277 Pages
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9.4.2
Test Environment
Figure 9-3 shows a test environment example. Test vectors are sent and interpreted by the tester. In this example,
the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to
form a single scan chain.
Figure 9-3. Application Test Environment Example
JTAG
Interface
Test Adaptor
Tester
ICE/JTAG Chip n
Chip 2
SAM9G46
Chip 1
SAM9G46-based Application Board In Test
9.5 Debug and Test Pin Description
Table 9-1.
Pin Name
Debug and Test Pin List
Function
NRST
TST
Microprocessor Reset
Test Mode Select
NTRST
TCK
TDI
TDO
TMS
RTCK
JTAGSEL
Test Reset Signal
Test Clock
Test Data In
Test Data Out
Test Mode Select
Returned Test Clock
JTAG Selection
DRXD
DTXD
Debug Receive Data
Debug Transmit Data
Reset/Test
ICE and JTAG
Debug Unit
Type
Input/Output
Input
Input
Input
Input
Output
Input
Output
Input
Input
Output
Active Level
Low
High
Low
SAM9G46 Series [DATASHEET]
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Atmel-11028G-ATARM-SAM9G46-Datasheet_08-Dec-15
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