DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
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DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—
19.5.1.26SDA Hold (IC_SDA_HOLD)—Offset 7Ch ...................................... 760
19.5.1.27Transmit Abort Source (IC_TX_ABRT_SOURCE)—Offset 80h.......... 761
19.5.1.28Enable Status (IC_ENABLE_STATUS)—Offset 9Ch ........................ 762
19.5.1.29SS and FS Spike Suppression Limit (IC_FS_SPKLEN)—Offset A0h .. 763
19.5.2 GPIO Controller Memory Mapped Registers............................................... 763
19.5.2.1 Port A Data (GPIO_SWPORTA_DR)—Offset 0h ............................. 764
19.5.2.2 Port A Data Direction (GPIO_SWPORTA_DDR)—Offset 4h.............. 764
19.5.2.3 Interrupt Enable (GPIO_INTEN)—Offset 30h ............................... 765
19.5.2.4 Interrupt Mask (GPIO_INTMASK)—Offset 34h ............................. 765
19.5.2.5 Interrupt Type (GPIO_INTTYPE_LEVEL)—Offset 38h ..................... 766
19.5.2.6 Interrupt Polarity (GPIO_INT_POLARITY)—Offset 3Ch .................. 767
19.5.2.7 Interrupt Status (GPIO_INTSTATUS)—Offset 40h......................... 767
19.5.2.8 Raw Interrupt Status (GPIO_RAW_INTSTATUS)—Offset 44h.......... 768
19.5.2.9 Debounce Enable (GPIO_DEBOUNCE)—Offset 48h ....................... 768
19.5.2.10Clear Interrupt (GPIO_PORTA_EOI)—Offset 4Ch .......................... 769
19.5.2.11Port A External Port (GPIO_EXT_PORTA)—Offset 50h ................... 770
19.5.2.12Synchronization Level (GPIO_LS_SYNC)—Offset 60h .................... 770
20.0 SPI Interface ........................................................................................................ 773
20.1 Signal Descriptions .......................................................................................... 773
20.2 Features ......................................................................................................... 773
20.2.1 SPI Controller....................................................................................... 773
20.2.1.1 Processor-Initiated Data Transfer .............................................. 774
20.2.1.2 Data Format ........................................................................... 774
20.2.1.3 FIFO Operation ....................................................................... 775
20.2.1.4 Baud Rate Generation .............................................................. 775
20.3 Register Map................................................................................................... 777
20.4 PCI Configuration Registers............................................................................... 778
20.4.1 Vendor ID (VENDOR_ID)—Offset 0h ........................................................ 778
20.4.2 Device ID (DEVICE_ID)—Offset 2h .......................................................... 779
20.4.3 Command Register (COMMAND_REGISTER)—Offset 4h .............................. 779
20.4.4 Status Register (STATUS)—Offset 6h....................................................... 780
20.4.5 Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h .................. 781
20.4.6 Cache Line Size (CACHE_LINE_SIZE)—Offset Ch ....................................... 781
20.4.7 Latency Timer (LATENCY_TIMER)—Offset Dh ............................................ 782
20.4.8 Header Type (HEADER_TYPE)—Offset Eh ................................................. 782
20.4.9 BIST (BIST)—Offset Fh .......................................................................... 782
20.4.10Base Address Register (BAR0)—Offset 10h ............................................... 783
20.4.11Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h....................... 784
20.4.12Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch ....................... 784
20.4.13Subsystem ID (SUB_SYS_ID)—Offset 2Eh................................................ 784
20.4.14Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h .............. 785
20.4.15Capabilities Pointer (CAP_POINTER)—Offset 34h ....................................... 785
20.4.16Interrupt Line Register (INTR_LINE)—Offset 3Ch ...................................... 785
20.4.17Interrupt Pin Register (INTR_PIN)—Offset 3Dh ......................................... 786
20.4.18MIN_GNT (MIN_GNT)—Offset 3Eh ........................................................... 786
20.4.19MAX_LAT (MAX_LAT)—Offset 3Fh ........................................................... 787
20.4.20Capability ID (PM_CAP_ID)—Offset 80h ................................................... 787
20.4.21Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h ............................ 787
20.4.22Power Management Capabilities (PMC)—Offset 82h ................................... 788
20.4.23Power Management Control/Status Register (PMCSR)—Offset 84h ............... 788
20.4.24PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset 86h...... 789
20.4.25Power Management Data Register (DATA_REGISTER)—Offset 87h............... 789
20.4.26Capability ID (MSI_CAP_ID)—Offset A0h.................................................. 790
20.4.27Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h .......................... 790
20.4.28Message Control (MESSAGE_CTRL)—Offset A2h ........................................ 790
20.4.29Message Address (MESSAGE_ADDR)—Offset A4h ...................................... 791
Intel® Quark SoC X1000
DS
26
October 2013
Document Number: 329676-001US
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