DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—Legacy Bridge
Bit
Default &
Range Access
Description
15
14:4
3
2
1
0
0b
RW/O
0b
RO
0b
RW/1C
0b
RW/1C
0b
RO
01h
RO
SPI Configuration Lock-Down (CLD): When set to 1, the SPI Static Configuration
information cannot be overwritten. Once set to 1, this bit can only be cleared by a
hardware reset
Reserved (RSV2): Reserved.
Blocked Access Status (BA): Hardware sets this bit to 1 when an access is blocked
from running on the SPI interface due to one of the protection policies or when any of
the programmed cycle registers are written while a programmed access is already in
progress. This bit is set for both programmed accesses and direct memory reads that
get blocked. This bit remains asserted until cleared by software writing a 1 or hardware
reset.
Cycle Done Status (CD): Hardware sets this bit to 1 when the SPI Cycle completes
(i.e., SCIP bit is 0) after software sets the GO bit. This bit remains asserted until cleared
by software writing a 1 or hardware reset. When this bit is set and the SMI Enable bit in
the SPI Control register is set, an internal signal is asserted to the SMI# generation
block. Software must make sure this bit is cleared prior to enabling the SPI SMI#
assertion for a new programmed access. This bit gets set after the Status Register
Polling sequence completes after reset de-asserts. It is cleared before and during that
sequence.
Reserved (RSV1): Reserved.
Cycle In Progress (CIP): Hardware sets this bit when software sets the SPI Cycle Go
bit in the SPI Control register. This bit remains set until the cycle completes on the SPI
interface. Hardware automatically sets and clears this bit so that software can
determine when read data is valid and/or when it is safe to begin programming the next
command. Software must only program the next command when this bit is 0. This bit
reports 1b during the Status Register Polling sequence after reset de-asserts; it is
cleared when that sequence completes.
21.7.4.2 SPI Control (SPICTL)—Offset 3022h
Access Method
Type: Memory Mapped I/O Register
(Size: 16 bits)
SPICTL: [RCBA] + 3022h
RCBA Type: PCI Configuration Register (Size: 32 bits)
RCBA Reference: [B:0, D:31, F:0] + F0h
Default: 4001h
15
12
8
4
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Bit
Default &
Range Access
Description
15
0b
RW
SMI# Enable (SMIEN): When set to 1, the SPI asserts an SMI# request whenever the
Cycle Done Status bit is 1.
14
1b
RW
Data Cycle (DC): When set to 1, there is data that corresponds to this transaction.
When 0, no data is delivered for this cycle, and the DBC and data fields themselves are
don't care.
Data Byte Count (DBCNT): Data Byte Count: This field specifies the number of bytes
13:8
0b
RW
to shift in or out during the data portion of the SPI cycle. The valid settings (in decimal)
are any value from 0 to 63. The number of bytes transferred is the value of this field
plus 1. Note that when this field is 00_0000b, then there is 1 byte to transfer and that
11_1111b means there are 64 bytes to transfer.
Intel® Quark SoC X1000
DS
844
October 2013
Document Number: 329676-001US
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