ST7LITEU05 ST7LITEU09
LITE TIMER (Cont’d)
Input Capture
The 8-bit input capture register is used to latch the
free-running upcounter after a rising or falling edge
is detected on the LTIC pin. When an input capture
occurs, the ICF bit is set and the LTICR register
contains the MSB of the free-running upcounter.
An interrupt is generated if the ICIE bit is set. The
ICF bit is cleared by reading the LTICR register.
The LTICR is a read only register and always con-
tains the data from the last input capture. Input
capture is inhibited if the ICF bit is set.
11.1.4 Low Power Modes
Mode
WAIT
ACTIVE-HALT
HALT
Description
No effect on Lite timer
No effect on Lite timer
Lite timer stops counting
11.1.5 Interrupts
Interrupt
Event
Timebase
Event
IC Event
Event
Flag
TBF
ICF
Enable
Control
Bit
TBIE
ICIE
Exit Exit
from from
Wait Halt
Yes No
Yes No
Exit
from
Active-
Halt
Yes
No
Note: The TBF and ICF interrupt events are con-
nected to separate interrupt vectors (see Inter-
rupts chapter).
They generate an interrupt if the enable bit is set in
the LTCSR register and the interrupt mask in the
CC register is reset (RIM instruction).
Figure 36. Input Capture Timing Diagram
125ns
(@ 8MHz fOSC)
fCPU
fOSC
13-bit COUNTER 0001h 0002h 0003h 0004h 0005h 0006h 0007h
LTIC PIN
ICF FLAG
LTICR REGISTER
xxh
04h
CLEARED
BY S/W
READING
LTIC REGISTER
07h
t
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