dsPIC33EVXXXGM00X/10X FAMILY
FIGURE 3-2:
PROGRAMMER’S MODEL
Working/Address
Registers
DSP Operand
Registers
DSP Address
Registers
PUSH.s and POP.s Shadows
Nested DO Stack
DSP
Accumulators(1)
AD39
ACCA
ACCB
D15
D0
D15
D0
D15
D0
W0 (WREG) W0 W0
W1 W1 W1
W2 W2 W2
W3 W3 W3
W4 W4 W4
W5 W5 W5
W6 W6 W6
W7 W7 W7
W8 W8 W8
W9 W9 W9
W10 W10 W10
W11 W11 W11
W12 W12 W12
W13 W13 W13
Frame Pointer/W14 W14 W14
Stack Pointer/W15 0
Alternate
Working/Address
Registers
SPLIM
0
Stack Pointer Limit
AD31
AD15
AD0
PC23
0
PC0
0
Program Counter
7
0
TBLPAG
9
0
DSRPAG
Data Table Page Address
X Data Space Read Page Address
15
RCOUNT
15
DCOUNT
0
REPEAT Loop Counter
0
DO Loop Counter and Stack
23
0
DOSTART
0
0
DO Loop Start Address and Stack
23
0
0
DOEND
0
DO Loop End Address and Stack
15
CORCON
0
CPU Core Control Register
SRL
OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C
STATUS Register
DS70005144E-page 24
2013-2016 Microchip Technology Inc.