DSPIC33EV64GM102-I/SO View Datasheet(PDF) - Microchip Technology
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DSPIC33EV64GM102-I/SO
Microchip Technology
DSPIC33EV64GM102-I/SO Datasheet PDF : 500 Pages
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dsPIC33EVXXXGM00X/10X FAMILY
4.3.3
DATA MEMORY ARBITRATION AND
BUS MASTER PRIORITY
EDS accesses from bus masters in the system are
arbitrated.
The arbiter for data memory (including EDS) arbitrates
between the CPU, the DMA and the MPLAB® ICD
module. In the event of coincidental access to a bus by
the bus masters, the arbiter determines which bus
master access has the highest priority. The other bus
masters are suspended and processed after the
access of the bus by the bus master with the highest
priority.
By default, the CPU is Bus Master 0 (M0) with the
highest priority and the MPLAB ICD is Bus Master 4
(M4) with the lowest priority. The remaining bus master
(DMA Controller) is allocated to M3 (M1 and M2 are
reserved and cannot be used). The user application
may raise or lower the priority of the DMA Controller to
be above that of the CPU by setting the appropriate bits
in the EDS Bus Master Priority Control (MSTRPR)
register. All bus masters with raised priorities will
maintain the same priority relationship relative to each
other (i.e., M1 being highest and M3 being lowest, with
M2 in between). Also, all the bus masters with priorities
FIGURE 4-13:
ARBITER ARCHITECTURE
below that of the CPU maintain the same priority
relationship relative to each other. The priority schemes
for bus masters with different MSTRPR values are
listed in Table 4-44.
Figure 4-13 shows the arbiter architecture.
The bus master priority control allows the user
application to manipulate the real-time response of the
system, either statically during initialization or
dynamically in response to real-time events.
TABLE 4-44: DATA MEMORY BUS
ARBITER PRIORITY
Priority
MSTRPR<15:0> Bit Setting(1)
0x0000
0x0020
M0 (highest)
CPU
DMA
M1
Reserved
CPU
M2
Reserved
Reserved
M3
M4 (lowest)
DMA
MPLAB® ICD
Reserved
MPLAB ICD
Note 1: All other values of MSTRPR<15:0> are
reserved.
DMA
Reserved
MPLAB® ICD
CPU
MSTRPR<15:0>
M0 M1 M2 M3 M4
Data Memory Arbiter
SRAM
2013-2016 Microchip Technology Inc.
DS70005144E-page 73
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