T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.
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T2080NXE8MQLB Datasheet PDF : 186 Pages
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Table 5. PROG_SFP timing 5 (continued)
Electrical characteristics
Driver type
Min
Max
Unit
Notes
tPROG_SFP_PROG
tPROG_SFP_VDD
tPROG_SFP_RST
Notes:
0
—
μs
2
0
—
μs
3
0
—
μs
4
1. Delay required from the deassertion of PORESET_B to driving PROG_SFP ramp up. Delay measured from PORESET_B
deassertion at 90% OVDD to 10% PROG_SFP ramp up.
2. Delay required from fuse programming finished to PROG_SFP ramp down start. Fuse programming must complete while
PROG_SFP is stable at 1.80 V. No activity other than that required for secure boot fuse programming is permitted while
PROG_SFP driven to any voltage above GND, including the reading of the fuse block. The reading of the fuse block may
only occur while PROG_SFP = GND. After fuse programming is completed, it is required to return PROG_SFP = GND.
3. Delay required from PROG_SFP ramp down complete to VDD ramp down start. PROG_SFP must be grounded to
minimum 10% PROG_SFP before VDD is at 90% VDD.
4. Delay required from PROG_SFP ramp down complete to PORESET_B assertion. PROG_SFP must be grounded to
minimum 10% PROG_SFP before PORESET_B assertion reaches 90% OVDD.
5. Only two secure boot fuse programming events are permitted per lifetime of a device.
3.3 Power-down requirements
The power-down cycle must complete such that power supply values are below 0.4 V
before a new power-up cycle can be started.
If performing secure boot fuse programming per Power sequencing, it is required that
PROG_SFP = GND before the system is power cycled (PORESET_B assertion) or
powered down (VDD ramp down) per the required timing specified in Table 5.
NOTE
All input signals, including I/Os that are configured as inputs,
driven into the chip need to monotonically increase/decrease
through entire rise/fall durations.
3.4 Power characteristics
This table shows the power dissipations of the VDD and SnVDD supply for various
operating platform clock frequencies versus the core and DDR clock frequencies when
Altivec power is gated off. See the e6500 core reference manual, section 8.6.1, "Altivec
power down—software controlled entry" for details on how to place Altivec in low
power state.
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors
51
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