AD9740-EB View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9740-EB Datasheet PDF : 32 Pages
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AD9740
In the differential input mode, the clock input functions as a
high impedance differential pair. The common-mode level of
the CLK+ and CLK− inputs can vary from 0.75 V to 2.25 V, and
the differential voltage can be as low as 0.5 V p-p. This mode
can be used to drive the clock with a differential sine wave
because the high gain bandwidth of the differential inputs
converts the sine wave into a single-ended square wave internally.
The final clock mode allows for a reduced external component
count when the DAC clock is distributed on the board using
PECL logic. The internal termination configuration is shown in
Figure 27. These termination resistors are untrimmed and can
vary up to ±20%. However, matching between the resistors
should generally be better than ±1%.
CLK+
CLK–
50Ω
AD9740
CLOCK
RECEIVER
50Ω
TO DAC CORE
VTT = 1.3V NOM
Figure 27. Clock Termination in PECL Mode
DAC TIMING
Input Clock and Data Timing Relationship
Dynamic performance in a DAC is dependent on the
relationship between the position of the clock edges and the
time at which the input data changes. The AD9740 is rising
edge triggered, and so exhibits dynamic performance sensitivity
when the data transition is close to this edge. In general, the
goal when applying the AD9740 is to make the data transition
close to the falling clock edge. This becomes more important as
the sample rate increases. Figure 28 shows the relationship of
SFDR to clock placement with different sample rates. Note that
at the lower sample rates, more tolerance is allowed in clock
placement, while at higher rates, more care must be taken.
75
70
65
60
20MHz SFDR
55
50MHz SFDR
50
45
40
50MHz SFDR
35
–3
–2
–1
0
1
2
3
ns
Figure 28. SFDR vs. Clock Placement @
fOUT = 20 MHz and 50 MHz (fCLOCK = 165 MSPS)
Sleep Mode Operation
The AD9740 has a power-down function that turns off the output
current and reduces the supply current to less than 6 mA over the
specified supply range of 2.7 V to 3.6 V and the temperature range.
This mode can be activated by applying a Logic Level 1 to the
SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 Ω
AVDD. This digital input also contains an active pull-down
circuit that ensures that the AD9740 remains enabled if this
input is left disconnected. The AD9740 takes less than 50 ns
to power down and approximately 5 μs to power back up.
POWER DISSIPATION
The power dissipation, PD, of the AD9740 is dependent on
several factors that include:
• The power supply voltages (AVDD, CLKVDD, and
DVDD)
• The full-scale current output (IOUTFS)
• The update rate (fCLOCK)
• The reconstructed digital input waveform
The power dissipation is directly proportional to the analog
supply current, IAVDD, and the digital supply current, IDVDD. IAVDD
is directly proportional to IOUTFS, as shown in Figure 29, and is
insensitive to fCLOCK. Conversely, IDVDD is dependent on both the
digital input waveform, fCLOCK, and digital supply DVDD. Figure 30
shows IDVDD as a function of full-scale sine wave output ratios
(fOUT/fCLOCK) for various update rates with DVDD = 3.3 V.
Rev. B | Page 16 of 32
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