C8051F045 データシートの表示（PDF） - Silicon Laboratories

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C8051F045

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F040/1/2/3/4/5/6/7

13.1. Power-On Reset

The C8051F04x family incorporates a power supply monitor that holds the MCU in the reset state until VDD

rises above the VRST level during power-up. See Figure 13.2 for timing diagram, and refer to Table 13.1 for

the Electrical Characteristics of the power supply monitor circuit. The /RST pin is asserted low until the end

of the 100 ms VDD Monitor timeout in order to allow the VDD supply to stabilize. The VDD Monitor reset is

enabled and disabled using the external VDD monitor enable pin (MONEN).

On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. All of the other

reset flags in the RSTSRC register are indeterminate. PORSF is cleared by all other resets. Since all

resets cause program execution to begin at the same location (0x0000), software can read the PORSF

flag to determine if a power-up was the cause of reset. The contents of internal data memory should be

assumed to be undefined after a power-on reset.

2.70

2.55

2.0

1.0

VRST

Logic HIGH

/RST

Logic LOW

Reset Time

Delay

t

Reset Time

Delay

Power-On Reset

VDD Monitor Reset

Figure 13.2. Reset Timing

13.2. Power-Fail Reset

When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply

monitor will drive the /RST pin low and return the CIP-51 to the reset state. When VDD returns to a level

above VRST, the CIP-51 will leave the reset state in the same manner as that for the power-on reset (see

Figure 13.2). Note that even though internal data memory contents are not altered by the power-fail reset,

it is impossible to determine if VDD dropped below the level required for data retention. If the PORSF flag is

set to logic 1, the data may no longer be valid.

13.3. External Reset

The external /RST pin provides a means for external circuitry to force the MCU into a reset state. Asserting

the /RST pin low will cause the MCU to enter the reset state. It may be desirable to provide an external pul-

166

Rev. 1.5

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