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7410

  

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7410 [Triple 3-input NAND gate ]

other parts : 74HC10D  74HC10DB  74HC10PW  74HC10U  74HCT10D  74HCT10DB  74HCT10PW  74HCT10U  74HC10  74HCT10 

Philips
Philips Electronics

GENERAL DESCRIPTION
The 74HC/HCT10 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT10 provide the 3-input NAND function.

FEATURES
• Output capability: standard
• ICC category: SSI

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7410 [TRIPLE 3-INPUT POSITIVE-NAND GATES ]

other parts : JM38510-00103BCA  JM38510-00103BDA  JM38510-07005BCA  JM38510-07005BDA  JM38510-30005B2A  JM38510-30005BCA  JM38510-30005BDA  JM38510-30005SCA  JM38510-30005SDA  SN5410J 

TI
Texas Instruments

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7410 [Triple 3-Input NAND Gates ]

other parts : 5410  5410DMQB  5410FMQB  DM5410  DM5410J  DM5410W  DM7410  DM7410N 

National-Semiconductor
National ->Texas Instruments

General Description
This device contains three independent gates each of which performs the logic NAND function.

Features
■ Alternate Military/Aerospace device (5410) is available.
   Contact a National Semiconductor Sales Office/Distributor for specifications.

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7410 [TRIPLE 3-INPUT NAND GATE LOW POWER SCHOTTKY ]

other parts : 74LS10  SN54LS10J  SN74LS10D  SN74LS10N 

Motorola
Motorola => Freescale

74140, SN74LS10N

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74107 [DUAL J-K FLIP FLOP WITH CLEAR ]

other parts : M54HC107  M54HC107F1R  M74HC107  M74HC107B1R  M74HC107C1R  M74HC107M1R 

ST-Microelectronics
STMicroelectronics

DESCRIPTION
The M54/74HC107 is a high speed CMOS DUAL JK FLIPFLOP fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. These flip-flop are edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, CLOCK, and CLEAR input and Q and Q outputs. CLEAR is independent of the clock and accomplished by a logic low on the input. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

. HIGH SPEED
   fMAX = 75 MHz (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
   ICC = 2 µA (MAX.) AT TA = 25°C
. HIGH NOISE IMMUNITY
   VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
  |IOH|= IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE WITH 54/74LS107

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74109 [Dual J-K Positive-Edge-Triggered Flip-Flops With Preset and Clear ]

other parts : 74LS109A  JM38510/30109B2A  JM38510/30109BEA  JM38510/30109BFA  JM38510/30109SEA  JM38510/30109SFA  LS109A  M38510/30109B2A  M38510/30109BEA  M38510/30109BFA 

TI
Texas Instruments

These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse.

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