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74109 [Dual J-K Positive-Edge-Triggered Flip-Flops With Preset and Clear ]

other parts : LS109A  74LS109A  SN74LS109AN3  SNJ54LS109AW  SNJ54LS109AJ  SN74LS109ADR  SN74LS109ADG4  SN74LS109ADE4  SN74LS109ANSR  SN74LS109ANE4 

Texas Instruments

These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse.

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