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PGA113

  

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PGA113 [Zerø-Drift Programmable Gain Amplifier With Mux ]

other parts : PGA112  PGA116  PGA117  PGA116AIPW  PGA117AIPW  PGA117AIPWR  PGA116AIPWR  PGA112AIDGSR  PGA113AIDGST  PGA116AIPWG4 

TI
Texas Instruments

Description
The PGA112 and PGA113 devices (binary and scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in a 10-pin, VSSOP package. The PGA116 and PGA117 (binary and scope gains) offer 10 analog inputs, a SPI interface with daisy-chain capability, and hardware and software shutdown in a 20-pin TSSOP package.
All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100, and 200.

Features
• Rail-to-Rail Input and Output
• Offset: 25 μV (Typical), 100 μV (Maximum)
• Zerø Drift: 0.35 μV/°C (Typical), 1.2 μV/°C (Maximum)
• Low Noise: 12 nV/√Hz
• Input Offset Current: ±5 nA Maximum (25°C)
• Gain Error: 0.1% Maximum (G ≤ 32), 0.3% Maximum (G > 32)
• Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128 (PGA112, PGA116)
• Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200 (PGA113, PGA117)
• Gain Switching Time: 200 ns
• 2 Channel MUX: PGA112, PGA113
   10 Channel MUX: PGA116, PGA117
• Four Internal Calibration Channels
• Amplifier Optimized for Driving CDAC ADCs
• Output Swing: 50 mV to Supply Rails
• AVDD and DVDD for Mixed Voltage Systems
• IQ = 1.1 mA (Typical)
• Software and Hardware Shutdown: IQ ≤ 4 μA (Typical)
• Temperature Range: –40°C to 125°C
• SPI™ Interface (10 MHz) With Daisy-Chain Capability

Applications
• Remote e-Meter Reading
• Automatic Gain Control
• Portable Data Acquisition
• PC-Based Signal Acquisition Systems
• Test and Measurement
• Programmable Logic Controllers
• Battery-Powered Instruments Handheld Test Equipment

View
PGA113AIDGSR [Zerø-Drift Programmable Gain Amplifier With Mux ]

other parts : PGA112  PGA113  PGA116  PGA117  PGA117AIPW  PGA116AIPW  PGA116AIPWR  PGA117AIPWR  PGA116AIPWG4  PGA113AIDGST 

TI
Texas Instruments

Description
The PGA112 and PGA113 devices (binary and scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in a 10-pin, VSSOP package. The PGA116 and PGA117 (binary and scope gains) offer 10 analog inputs, a SPI interface with daisy-chain capability, and hardware and software shutdown in a 20-pin TSSOP package.
All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100, and 200.

Features
• Rail-to-Rail Input and Output
• Offset: 25 μV (Typical), 100 μV (Maximum)
• Zerø Drift: 0.35 μV/°C (Typical), 1.2 μV/°C (Maximum)
• Low Noise: 12 nV/√Hz
• Input Offset Current: ±5 nA Maximum (25°C)
• Gain Error: 0.1% Maximum (G ≤ 32), 0.3% Maximum (G > 32)
• Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128 (PGA112, PGA116)
• Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200 (PGA113, PGA117)
• Gain Switching Time: 200 ns
• 2 Channel MUX: PGA112, PGA113
   10 Channel MUX: PGA116, PGA117
• Four Internal Calibration Channels
• Amplifier Optimized for Driving CDAC ADCs
• Output Swing: 50 mV to Supply Rails
• AVDD and DVDD for Mixed Voltage Systems
• IQ = 1.1 mA (Typical)
• Software and Hardware Shutdown: IQ ≤ 4 μA (Typical)
• Temperature Range: –40°C to 125°C
• SPI™ Interface (10 MHz) With Daisy-Chain Capability

Applications
• Remote e-Meter Reading
• Automatic Gain Control
• Portable Data Acquisition
• PC-Based Signal Acquisition Systems
• Test and Measurement
• Programmable Logic Controllers
• Battery-Powered Instruments Handheld Test Equipment

View
PGA113AIDGST [Zerø-Drift Programmable Gain Amplifier With Mux ]

other parts : PGA112  PGA113  PGA116  PGA117  PGA117AIPW  PGA116AIPW  PGA116AIPWR  PGA117AIPWR  PGA116AIPWG4  PGA113AIDGSR 

TI
Texas Instruments

Description
The PGA112 and PGA113 devices (binary and scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in a 10-pin, VSSOP package. The PGA116 and PGA117 (binary and scope gains) offer 10 analog inputs, a SPI interface with daisy-chain capability, and hardware and software shutdown in a 20-pin TSSOP package.
All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100, and 200.

Features
• Rail-to-Rail Input and Output
• Offset: 25 μV (Typical), 100 μV (Maximum)
• Zerø Drift: 0.35 μV/°C (Typical), 1.2 μV/°C (Maximum)
• Low Noise: 12 nV/√Hz
• Input Offset Current: ±5 nA Maximum (25°C)
• Gain Error: 0.1% Maximum (G ≤ 32), 0.3% Maximum (G > 32)
• Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128 (PGA112, PGA116)
• Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200 (PGA113, PGA117)
• Gain Switching Time: 200 ns
• 2 Channel MUX: PGA112, PGA113
   10 Channel MUX: PGA116, PGA117
• Four Internal Calibration Channels
• Amplifier Optimized for Driving CDAC ADCs
• Output Swing: 50 mV to Supply Rails
• AVDD and DVDD for Mixed Voltage Systems
• IQ = 1.1 mA (Typical)
• Software and Hardware Shutdown: IQ ≤ 4 μA (Typical)
• Temperature Range: –40°C to 125°C
• SPI™ Interface (10 MHz) With Daisy-Chain Capability

Applications
• Remote e-Meter Reading
• Automatic Gain Control
• Portable Data Acquisition
• PC-Based Signal Acquisition Systems
• Test and Measurement
• Programmable Logic Controllers
• Battery-Powered Instruments Handheld Test Equipment

View
PGA113AIDGSRG4 [Zerø-Drift Programmable Gain Amplifier With Mux ]

other parts : PGA112  PGA113  PGA116  PGA117  PGA116AIPW  PGA117AIPW  PGA116AIPWR  PGA117AIPWR  PGA113AIDGSR  PGA112AIDGST 

TI
Texas Instruments

Description
The PGA112 and PGA113 devices (binary and scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in a 10-pin, VSSOP package. The PGA116 and PGA117 (binary and scope gains) offer 10 analog inputs, a SPI interface with daisy-chain capability, and hardware and software shutdown in a 20-pin TSSOP package.
All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100, and 200.

Features
• Rail-to-Rail Input and Output
• Offset: 25 μV (Typical), 100 μV (Maximum)
• Zerø Drift: 0.35 μV/°C (Typical), 1.2 μV/°C (Maximum)
• Low Noise: 12 nV/√Hz
• Input Offset Current: ±5 nA Maximum (25°C)
• Gain Error: 0.1% Maximum (G ≤ 32), 0.3% Maximum (G > 32)
• Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128 (PGA112, PGA116)
• Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200 (PGA113, PGA117)
• Gain Switching Time: 200 ns
• 2 Channel MUX: PGA112, PGA113
   10 Channel MUX: PGA116, PGA117
• Four Internal Calibration Channels
• Amplifier Optimized for Driving CDAC ADCs
• Output Swing: 50 mV to Supply Rails
• AVDD and DVDD for Mixed Voltage Systems
• IQ = 1.1 mA (Typical)
• Software and Hardware Shutdown: IQ ≤ 4 μA (Typical)
• Temperature Range: –40°C to 125°C
• SPI™ Interface (10 MHz) With Daisy-Chain Capability

Applications
• Remote e-Meter Reading
• Automatic Gain Control
• Portable Data Acquisition
• PC-Based Signal Acquisition Systems
• Test and Measurement
• Programmable Logic Controllers
• Battery-Powered Instruments Handheld Test Equipment

View
PGA113AIDGSTG4 [Zerø-Drift Programmable Gain Amplifier With Mux ]

other parts : PGA112  PGA113  PGA116  PGA117  PGA116AIPW  PGA117AIPW  PGA116AIPWR  PGA117AIPWR  PGA113AIDGSR  PGA112AIDGST 

TI
Texas Instruments

Description
The PGA112 and PGA113 devices (binary and scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in a 10-pin, VSSOP package. The PGA116 and PGA117 (binary and scope gains) offer 10 analog inputs, a SPI interface with daisy-chain capability, and hardware and software shutdown in a 20-pin TSSOP package.
All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100, and 200.

Features
• Rail-to-Rail Input and Output
• Offset: 25 μV (Typical), 100 μV (Maximum)
• Zerø Drift: 0.35 μV/°C (Typical), 1.2 μV/°C (Maximum)
• Low Noise: 12 nV/√Hz
• Input Offset Current: ±5 nA Maximum (25°C)
• Gain Error: 0.1% Maximum (G ≤ 32), 0.3% Maximum (G > 32)
• Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128 (PGA112, PGA116)
• Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200 (PGA113, PGA117)
• Gain Switching Time: 200 ns
• 2 Channel MUX: PGA112, PGA113
   10 Channel MUX: PGA116, PGA117
• Four Internal Calibration Channels
• Amplifier Optimized for Driving CDAC ADCs
• Output Swing: 50 mV to Supply Rails
• AVDD and DVDD for Mixed Voltage Systems
• IQ = 1.1 mA (Typical)
• Software and Hardware Shutdown: IQ ≤ 4 μA (Typical)
• Temperature Range: –40°C to 125°C
• SPI™ Interface (10 MHz) With Daisy-Chain Capability

Applications
• Remote e-Meter Reading
• Automatic Gain Control
• Portable Data Acquisition
• PC-Based Signal Acquisition Systems
• Test and Measurement
• Programmable Logic Controllers
• Battery-Powered Instruments Handheld Test Equipment

View
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