Integrated circuits, Transistor, Semiconductors Free Datasheet Search and Download Site

SN74LS12

  

Datasheet

Match, Like SN74LS12 SN74LS122 SN74LS123 SN74LS128 SN74LS12D SN74LS12N
Start with SN74LS122* SN74LS123* SN74LS125* SN74LS126* SN74LS128* SN74LS12D* SN74LS12N*
End N/A
Included N/A
View Details    
SN74LS12 [TRIPLE 3-INPUT POSITIVE-NAND GATES WITH OPEN-COLLECTOR OUTPUTS ]

other parts : 74LS12  SN5412  SN7412  SN5412J  SN5412W  SN7412N  SN54LS12  SN54LS12W  SN54LS12J  SN74LS12N 

TI
Texas Instruments


View
SN74LS128 [TRIPLE 3-INPUT POSITIVE-NAND GATES WITH COLLECTOR OUTPUTS ]

other parts : 74LS128  74LS128N 

TI
Texas Instruments

 

View
SN74LS12D [TRIPLE 3-INPUT POSITIVE-NAND GATES WITH OPEN-COLLECTOR OUTPUTS ]

other parts : 74LS12  SN5412  SN7412  SN5412J  SN5412W  SN7412N  SN74LS12  SN54LS12  SN54LS12J  SN54LS12W 

TI
Texas Instruments


View
SN74LS12N [TRIPLE 3-INPUT POSITIVE-NAND GATES WITH OPEN-COLLECTOR OUTPUTS ]

other parts : 74LS12  SN5412  SN7412  SN5412J  SN5412W  SN7412N  SN74LS12  SN54LS12  SN54LS12J  SN54LS12W 

TI
Texas Instruments


View
SN74LS122 [Retriggerable monostable multivibrator ]

other parts : 74LS122  74LS123  54LS122  54LS123  SN54LS122  SN54LS123  SN74LS123  SN74LS123D  SN74LS122D  SN54LS123J 

Motorola
Motorola => Freescale

These dc triggered multivibrators feature pulse width control by three methods. The basic pulse width is programmed by selection of external resistance and capacitance values. The LS122 has an internal timing resistor that allows the circuits to be used with only an external capacitor. Once triggered, the basic pulse width may be extended by retriggering the gated low-level-active (A) or high-level-active (B) inputs, or be reduced by use of the overriding clear.

• Overriding Clear Terminates Output Pulse
• Compensated for VCC and Temperature Variations
• DC Triggered from Active-High or Active-Low Gated Logic Inputs
• Retriggerable for Very Long Output Pulses, up to 100% Duty Cycle
• Internal Timing Resistors on LS122

View
SN74LS123 [Retriggerable monostable multivibrator ]

other parts : 74LS122  74LS123  54LS122  54LS123  SN54LS122  SN54LS123  SN74LS122  SN74LS123D  SN74LS122N  SN54LS123J 

Motorola
Motorola => Freescale

These dc triggered multivibrators feature pulse width control by three methods. The basic pulse width is programmed by selection of external resistance and capacitance values. The LS122 has an internal timing resistor that allows the circuits to be used with only an external capacitor. Once triggered, the basic pulse width may be extended by retriggering the gated low-level-active (A) or high-level-active (B) inputs, or be reduced by use of the overriding clear.

• Overriding Clear Terminates Output Pulse
• Compensated for VCC and Temperature Variations
• DC Triggered from Active-High or Active-Low Gated Logic Inputs
• Retriggerable for Very Long Output Pulses, up to 100% Duty Cycle
• Internal Timing Resistors on LS122

View
SN74LS125D [QUAD 3-STATE BUFFERS ]

other parts : 54LS125  54LS126  74LS125  74LS126  SN54LS125  SN74LS126D  SN74LS125N  SN54LS126J  SN54LS125J  SN74LS126N 

Motorola
Motorola => Freescale

QUAD 3-STATE BUFFERS
LOW POWER SCHOTTKY

View
SN74LS125N [QUAD 3-STATE BUFFERS ]

other parts : 54LS125  54LS126  74LS125  74LS126  SN54LS125  SN74LS126D  SN74LS125D  SN54LS126J  SN54LS125J  SN74LS126N 

Motorola
Motorola => Freescale

QUAD 3-STATE BUFFERS
LOW POWER SCHOTTKY

View
SN74LS126A [Quad 3-State Buffers ]

other parts : 74LS125A  74LS126A  SN74LS125A  SN74LS126AD  SN74LS125AN  SN74LS125AM  SN74LS126AN  SN74LS125AD  SN74LS126AM  SN74LS125AMEL 

ON-Semiconductor
ON Semiconductor

Quad 3-State Buffers

LOW POWER SCHOTTKY

View
SN74LS126A [QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS ]

other parts : LS126A  LS125A  SN54126  SN54125  SN74125  SN74126  SN74125N  SN54126J  74LS126A  74LS125A 

TI
Texas Instruments

description
These bus buffers feature three-state outputs that, when enabled, have the low impedance characteristics of a TTL output with additional drive capability at high logic levels to permit driving heavily loaded bus lines without external pullup resistors. When disabled, both output transistors are turned off, presenting a high-impedance state to the bus so the output will act neither as a significant load nor as a driver. The ’125 and ’LS125A devices’ outputs are disabled when G is high. The ’126 and ’LS126A devices’ outputs are disabled when G is low.

● Quad Bus Buffers
● 3-State Outputs
● Separate Control for Each Channel

View
1
Share Link : 

HOME

Language : 한국어     日本語     русский     简体中文     español
@ 2015 - 2018  [ Home ][ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]