General Description
These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the quad (DM74S175) versions feature comple mentary outputs from each flip-flop.
Features
â DM74S174 contain six flip-flops with single-rail outputs.
â DM74S175 contain four flip-flops with double-rail outputs.
â Buffered clock and direct clear inputs
â Individual data input to each flip-flop
â Applications include:
Buffer/storage registers
Shift registers
Pattern generators
â Typical clock frequency 110 MHz
â Typical power dissipation per flip-flop 75mW
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