General Description
The FC106 Fibre Channel transceiver chip implements the lower layer protocols of the ANSI X3.230-1994 Fibre Channel standard. The Fibre Channel standard specifies the mapping of various upper layer protocols (ULP) such as SCSI, IP and HiPPI to a common lower layer protocol, together with appropriate electrical and optical high performance specifications. Fibre Channel provides a channel over which concurrent communication of a variety of ULPâs may exist on a single interconnect between workstations, mainframes and supercomputers, and provides a connection to mass storage devices and other peripherals.
FEATURES
â Serial Link Transceiver
â serializer and deserializer
â implementing the Fibre Channel FC0 and FC1 layers
â Direct support for 1.0625 GBaud Fibre Channel (ANSI X3.230-1994) rates
â Fibre Channel 10-bit Interface (ANSI TR/X3.18-199X)
â Direct interfaces to optical tranceivers
â Plesiochronous mode operation
â transmitter and receiver clock
frequencies may differ by up to 100 ppm
â Integrated Fibre Channel 8b/10b
encode/decode (optional use through JTAG)
â Byte and word synchronization of incoming serial stream
â Supports any DC-balanced encoding scheme
â Internal Loop-Back for Self-Test
â Random Pattern Auto-Test
â Optional integrated impedance
adaptation to transmission line characteristics (50 or 75 ohms)
â TTL compatible parallel I/Oâs
â JTAG Test Access Port
â 0.35µ CMOS Technology for low cost and low power
â PQFP package available in two sizes:
14x14 mm (FC106/14) or 10x10 mm (FC106/10)
APPLICATIONS
â Fibre Channel Arbitrated Loop
â Fibre Channel fabric
â Transmission schemes encoding
bytes as 10-bit characters to form a DC-balanced stream
â High performance backplane interconnect
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