Features
• Access Times of 60, 70, 90, 120, 150ns
• 100,000 Erase/Program Cycles Minimum
• Sector Architecture
- 8 equal size sectors of 64KBytes each
- Any combination of sectors can be concurrently erased. Also supports full chip erase
• Organized as 512Kx32
• Commercial, Industrial, and Military Temperature Ranges
• 5 Volt Read and Write
• Low Power CMOS
• Embedded erase and program algorithms
• TTL compatible inputs and CMOS outputs
• Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation.
• Page program operation and internal program control time
• Weight: WF512K32N-XH1X5 - 13 grams typical
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