FEATURES
â¾ Access Times of 60, 70, 90, 120, 150ns
â¾ Packaging
⢠32 pin, Hermetic Ceramic, 0.600" DIP
(Package 300)
⢠32 lead, Hermetic Ceramic, 0.400" SOJ
(Package 101)
⢠32 pin, Rectangular Ceramic Leadless Chip
Carrier (Package 601)
⢠32 lead Flatpack (Package 220)
â¾ 1,000,000 Erase/Program Cycles Minimum
â¾ Sector Erase Architecture
⢠8 equal size sectors of 64K bytes each
⢠Any combination of sectors can be concurrently
erased. Also supports full chip erase
â¾ Organized as 512Kx8
â¾ Commercial, Industrial and Military Temperature
Ranges
⾠5 Volt Programming. 5V ± 10% Supply.
â¾ Low Power CMOS
â¾ Embedded Erase and Program Algorithms
â¾ TTL Compatible Inputs and CMOS Outputs
â¾ Page Program Operation and Internal Program
Control Time.
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