Z8F012APJ020SG 查看數據表（PDF） - Zilog
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Z8F012APJ020SG Datasheet PDF : 282 Pages
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Z8 Encore! XP® F082A Series
Product Specification
65
Table 42. IRQ1 Enable High Bit Register (IRQ1ENH)
Bit
7
6
5
Field
PA7VENH PA6CENH PA5ENH
RESET
0
0
0
R/W
R/W
R/W
R/W
Address
4
3
PA4ENH PA3ENH
0
0
R/W
R/W
FC4H
2
PA2ENH
0
R/W
1
PA1ENH
0
R/W
0
PA0ENH
0
R/W
Bit
[7]
PA7VENH
[6]
PA6CENH
[5:0]
PAxENH
Description
Port A Bit[7] or LVD Interrupt Request Enable High Bit
Port A Bit[7] or Comparator Interrupt Request Enable High Bit
Port A Bit[x] Interrupt Request Enable High Bit
See the Shared Interrupt Select Register (IRQSS) Register on page 68 for selection of
either the LVD or the comparator as the interrupt source.
Table 43. IRQ1 Enable Low Bit Register (IRQ1ENL)
Bit
Field
RESET
R/W
Address
7
6
PA7VENL PA6CENL
0
0
R/W
R/W
5
PA5ENL
0
R/W
4
3
PA4ENL PA3ENL
0
0
R/W
R/W
FC5H
2
PA2ENL
0
R/W
1
PA1ENL
0
R/W
0
PA0ENL
0
R/W
Bit
[7]
PA7VENL
[6]
PA6CENL
[5:0]
PAxENL
Description
Port A Bit[7] or LVD Interrupt Request Enable Low Bit
Port A Bit[6] or Comparator Interrupt Request Enable Low Bit
Port A Bit[x] Interrupt Request Enable Low Bit
IRQ2 Enable High and Low Bit Registers
Table 44 describes the priority control for IRQ2. The IRQ2 Enable High and Low Bit reg-
isters, shown in Tables 44 and 45, form a priority-encoded enabling for interrupts in the
Interrupt Request 2 Register.
PS022827-1212
PRELIMINARY
Interrupt Control Register Definitions
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