Z8F012APJ020SG 查看數據表（PDF） - Zilog
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Z8F012APJ020SG Datasheet PDF : 282 Pages
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Z8 Encore! XP® F082A Series
Product Specification
66
Table 44. IRQ2 Enable and Priority Encoding
IRQ2ENH[x] IRQ2ENL[x] Priority
0
0
Disabled
0
1
Level 1
1
0
Level 2
1
1
Level 3
Note: x indicates register bits 0–7.
Description
Disabled
Low
Medium
High
Table 45. IRQ2 Enable High Bit Register (IRQ2ENH)
Bit
7
Field
RESET
0
R/W
R/W
Address
6
5
Reserved
0
0
R/W
R/W
4
3
C3ENH
0
0
R/W
R/W
FC7H
2
C2ENH
0
R/W
1
C1ENH
0
R/W
0
C0ENH
0
R/W
Bit
[7:4]
[3]
C3ENH
[2]
C2ENH
[1]
C1ENH
[0]
C0ENH
Description
Reserved
These bits are reserved and must be programmed to 0000.
Port C3 Interrupt Request Enable High Bit
Port C2 Interrupt Request Enable High Bit
Port C1 Interrupt Request Enable High Bit
Port C0 Interrupt Request Enable High Bit
PS022827-1212
PRELIMINARY
Interrupt Control Register Definitions
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