C8051F002 查看數據表（PDF） - Silicon Laboratories
零件编号
产品描述 (功能)
生产厂家
C8051F002 Datasheet PDF : 171 Pages
| |||
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 17.2. Typical SPI Interconnection
NSS
Slave
Device
NSS
Slave
Device
NSS
Slave
Device
VDD
Master
Device
MISO
MOSI
SCK
17.1. Signal Descriptions
The four signals used by the SPI (MOSI, MISO, SCK, NSS) are described below.
17.1.1. Master Out, Slave In
The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave devices. It is used to
serially transfer data from the master to the slave. Data is transferred most-significant bit first.
17.1.2. Master In, Slave Out
The master-in, slave-out (MISO) signal is an output from a slave device and an input to the master device. It is used
to serially transfer data from the slave to the master. Data is transferred most-significant bit first. A SPI slave
places the MISO pin in a high-impedance state when the slave is not selected.
17.1.3. Serial Clock
The serial clock (SCK) signal is an output from the master device and an input to slave devices. It is used to
synchronize the transfer of data between the master and slave on the MOSI and MISO lines.
17.1.4. Slave Select
The slave select (NSS) signal is an input used to select the SPI module when in slave mode by a master, or to
disable the SPI module when in master mode. When in slave mode, it is pulled low to initiate a data transfer and
remains low for the duration of the transfer.
Rev. 1.7
124
Share Link: 