C8051F002 查看數據表（PDF） - Silicon Laboratories

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C8051F002

Mixed-Signal 32KB ISP FLASH MCU Family

Silicon Laboratories 

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

in an “off-line” state. In a multiple-master environment, the system controller should check the state of the

SLVSEL flag (SPI0CN.2) to ensure the bus is free before setting the MSTEN bit and initiating a data transfer.

17.3. Serial Clock Timing

As shown in Figure 17.4, four combinations of serial clock phase and polarity can be selected using the clock

control bits in the SPI Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.7) selects one of two clock

phases (edge used to latch the data). The CKPOL bit (SPI0CFG.6) selects between an active-high or active-low

clock. Both master and slave devices must be configured to use the same clock phase and polarity. Note: the SPI

should be disabled (by clearing the SPIEN bit, SPI0CN.0) while changing the clock phase and polarity.

The SPI Clock Rate Register (SPI0CKR) as shown in Figure 17.7 controls the master mode serial clock frequency.

This register is ignored when operating in slave mode.

Figure 17.4. Data/Clock Timing Diagram

SCK

(CKPOL = 0, CKPHA = 0)

SCK

(CKPOL = 0, CKPHA = 1)

SCK

(CKPOL = 1, CKPHA = 0)

SCK

(CKPOL = 1, CKPHA = 1)

MISO/MOSI

MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB

NSS

Rev. 1.7

126

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