C8051F002 查看數據表（PDF） - Silicon Laboratories

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C8051F002

Mixed-Signal 32KB ISP FLASH MCU Family

Silicon Laboratories 

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

17.4. SPI Special Function Registers

The SPI is accessed and controlled through four special function registers in the system controller: SPI0CN Control

Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four

special function registers related to the operation of the SPI Bus are described in the following section.

Figure 17.5. SPI0CFG: SPI Configuration Register

R/W

CKPHA

Bit7

R/W

CKPOL

Bit6

R

BC2

Bit5

R

BC1

Bit4

R

BC0

Bit3

Bit7:

CKPHA: SPI Clock Phase.

This bit controls the SPI clock phase.

0: Data sampled on first edge of SCK period.

1: Data sampled on second edge of SCK period.

R/W

SPIFRS2

Bit2

R/W

SPIFRS1

Bit1

R/W

SPIFRS0

Bit0

Reset Value

00000111

SFR Address:

0x9A

Bit6:

CKPOL: SPI Clock Polarity.

This bit controls the SPI clock polarity.

0: SCK line low in idle state.

1: SCK line high in idle state.

Bits5-3: BC2-BC0: SPI Bit Count.

Indicates which of the up to 8 bits of the SPI word have been transmitted.

BC2-BC0

0

0

0

0

0

1

0

1

0

0

1

1

1

0

0

1

0

1

1

1

0

1

1

1

Bit Transmitted

Bit 0 (LSB)

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7 (MSB)

Bits2-0: SPIFRS2-SPIFRS0: SPI Frame Size.

These three bits determine the number of bits to shift in/out of the SPI shift register

during a data transfer in master mode. They are ignored in slave mode.

SPIFRS

0

0

0

0

0

1

0

1

0

0

1

1

1

0

0

1

0

1

1

1

0

1

1

1

Bits Shifted

1

2

3

4

5

6

7

8

.

127

Rev. 1.7

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