LTC3732CUHF 查看數據表（PDF） - Linear Technology

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LTC3732CUHF

3-Phase, 5-Bit VID, 600kHz, Synchronous Buck Switching Regulator Controller

Linear Technology 

LTC3732

APPLICATIO S I FOR ATIO

increasing current draw with increasing voltage. The EAIN

pin should be artificially held 70% above its nominal

operating level of 0.6V, or 0.42V in order to prevent the IC

from “folding back” the peak current level. A suggested

circuit is shown in Figure 8.

VCC

VCC

CALCULATE FOR

0.42V TO 0.55V

LTC3732

Q1

EAIN

3732 F08

Figure 8. Foldback Current Elimination

The emitter of Q1 will hold up the EAIN pin to a voltage in

the absence of VOUT that will prevent the internal sensing

circuitry from reducing the peak output current. Remov-

ing the function in this manner eliminates the external

MOSFET’s protective feature under short-circuit condi-

tions. This technique will also prevent the short-circuit

latchoff function from turning off the part during a short-

circuit event and the output current will only be limited to

N • 75mV/RSENSE.

Undervoltage Reset

In the event that the input power source to the IC (VCC)

drops below 4V, the RUN/SS capacitor will be discharged

to ground. When VCC rises above 4V, the RUN/SS capaci-

tor will be allowed to recharge and initiate another soft-

start turn-on attempt. This may be useful in applications

that switch between two supplies that are not diode

connected, but note that this cannot make up for the

resultant interruption of the regulated output.

Phase-Locked Loop and Frequency Synchronization

The IC has a phase-locked loop comprised of an internal

voltage controlled oscillator and phase detector. This

allows the top MOSFET of output stage 1’s turn-on to be

locked to the rising edge of an external source. The

frequency range of the voltage controlled oscillator is

±50% around the center frequency fO. A voltage applied to

the PLLFLTR pin of 1.2V corresponds to a frequency of

approximately 400kHz. The nominal operating frequency

range of the IC is 225kHz to 680kHz.

The phase detector used is an edge sensitive digital type

that provides zero degrees phase shift between the exter-

nal and internal oscillators. This type of phase detector will

not lock the internal oscillator to harmonics of the input

frequency. The PLL hold-in range, ∆fH, is equal to the

capture range, ∆fC:

∆fH = ∆fC = ±0.5 fO

The output of the phase detector is a complementary pair

of current sources charging or discharging the external

filter components on the PLLFLTR pin. A simplified block

diagram is shown in Figure 9.

EXTERNAL

OSC

PHASE

DETECTOR/

OSCILLATOR

OSC

RLP

2.4V

10k

CLP

PLLFLTR

PLLIN

DIGITAL

PHASE/

FREQUENCY

50k

DETECTOR

3732 F09

Figure 9. Phase-Locked Loop Block Diagram

If the external frequency (fPLLIN) is greater than the oscil-

lator frequency, fOSC, current is sourced continuously,

pulling up the PLLFLTR pin. When the external frequency

is less than fOSC, current is sunk continuously, pulling

down the PLLFLTR pin. If the external and internal fre-

quencies are the same, but exhibit a phase difference, the

current sources turn on for an amount of time correspond-

ing to the phase difference. Thus, the voltage on the

PLLFLTR pin is adjusted until the phase and frequency of

the external and internal oscillators are identical. At this

stable operating point, the phase comparator output is

open and the filter capacitor CLP holds the voltage. The IC

PLLIN pin must be driven from a low impedance source

such as a logic gate located close to the pin. When using

multiple ICs for a phase-locked system, the PLLFLTR pin

of the master oscillator should be biased at a voltage that

will guarantee the slave oscillator(s) ability to lock onto the

3732f

19

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