M48T08-100PC 查看數據表（PDF） - STMicroelectronics

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M48T08-100PC

CMOS 8K x 8 TIMEKEEPER SRAM

STMicroelectronics 

M48Z02, M48Z12

DATA RETENTION MODE

With valid VCC applied, the M48Z02,12 operates as

a conventional BYTEWIDE™ static RAM. Should

the supply voltage decay, the RAM will automat-

ically power-fail deselect, write protecting itself

when VCC falls within the VPFD(max), VPFD(min)

window. All outputs become high impedance, and

all inputs are treated as ”don’t care.”

Note: A power failure during a write cycle may

corrupt data at the currently addressed location, but

does not jeopardize the rest of the RAM’s content.

At voltages below VPFD(min), the user can be as-

sured the memory will be in a write protected state,

provided the VCC fall time is not less than tF. The

M48Z02,12 may respond to transient noise spikes

on VCC that reach into the deselect window during

the time the device is sampling VCC. Therefore,

decoupling of the power supply lines is recom-

mended.

The power switching circuit connects external VCC

to the RAM and disconnects the battery when VCC

rises above VSO. As VCC rises, the battery voltage

is checked. If the voltage is too low, an internal

Battery Not OK (BOK) flag will be set. The BOK flag

can be checked after power up. If the BOK flag is

set, the first write attempted will be blocked. The

flag is automatically cleared after the first write, and

normal RAM operation resumes. Figure 9 illus-

trates how a BOK check routine could be struc-

tured.

Figure 9. Checking the BOK Flag Status

POWER-UP

READ DATA

AT ANY ADDRESS

WRITE DATA

COMPLEMENT BACK

TO SAME ADDRESS

READ DATA

AT SAME

ADDRESS AGAIN

IS DATA

COMPLEMENT

OFFIRST

READ?

(BATTERY OK) YES

WRITE ORIGINAL

DATA BACK TO

SAME ADDRESS

NO (BATTERY LOW)

NOTIFY SYSTEM

OF LOW BATTERY

(DATA MAY BE

CORRUPTED)

CONTINUE

AI00607

9/12

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