PIC18F2685T-I/SP 查看數據表（PDF） - Microchip Technology
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PIC18F2685T-I/SP
Microchip Technology
PIC18F2685T-I/SP Datasheet PDF : 484 Pages
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PIC18F2682/2685/4682/4685
FIGURE 27-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
70
71
72
80
MSb
78
79
bit 6 - - - - - -1
75, 76
SDI
MSb In
bit 6 - - - -1
74
73
Note: Refer to Figure 27-4 for load conditions.
83
79
78
LSb
77
LSb In
TABLE 27-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SS ↓ to SCK ↓ or SCK ↑ Input
TSSL2SCL
TCY
—
71
TSCH
SCK Input High Time
Continuous 1.25 TCY + 30 —
71A
Single Byte
40
—
72
TSCL
SCK Input Low Time
Continuous 1.25 TCY + 30 —
72A
Single Byte
40
—
73
TDIV2SCH, Setup Time of SDI Data Input to SCK Edge
TDIV2SCL
100
—
73A TB2B
Last Clock Edge of Byte1 to the First Clock Edge of Byte 2 1.5 TCY + 40 —
74
TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
100
—
75
TDOR
SDO Data Output Rise Time
PIC18FXXXX
—
25
PIC18LFXXXX
—
45
76
TDOF
SDO Data Output Fall Time
—
25
77
TSSH2DOZ SS ↑ to SDO Output High-Impedance
10
50
80
TSCH2DOV, SDO Data Output Valid after SCK Edge PIC18FXXXX
—
50
TSCL2DOV
PIC18LFXXXX
—
100
83
TscH2ssH, SS ↑ after SCK Edge
TscL2ssH
1.5 TCY + 40 —
Note 1: Requires the use of parameter 73A.
2: Only if parameter 71A and 72A are used.
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns
ns (Note 2)
ns
ns
ns VDD = 2.0V
ns
ns
ns
ns VDD = 2.0V
ns
DS39761B-page 444
Preliminary
© 2007 Microchip Technology Inc.
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