Z8018033FSG 查看數據表（PDF） - Zilog
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Z8018033FSG Datasheet PDF : 85 Pages
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Z80180
Microprocessor Unit
35
E Clock Timing (Memory READ/WRITE Cycle, I/O READ/WRITE Cycle)
T1
T2
TW
ø
E
(Memory READ/WRITE)
49
49
E
(I/O READ)
49
E
(I/O WRITE)
TW
T3
50
50
50
15
16
D0–D7
Figure 20. E Clock Timing (Memory R/W Cycle, I/O R/W Cycle)
E
PH1ø
E
49
50
BUS RELEASE mode
SLEEP mode
SYSTEM STOP mode
Figure 21. E Clock Timing (Bus Release, Sleep, System Stop Modes
E Clock Timing (Bus Release, Sleep, System Stop Modes)
E Clock Timing (Minimum timing example of
T2
TW
T3
T1
T2
E
Example
I/O READ
→ Opcode Fetch
50 52
49
50
49
54
53
51
53
54
Figure 22. E Clock Timing (PWEL and PWEH Minimum Timing)
PS014004-1106
Architecture
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