AT91SAM9G46B-CU 查看數據表（PDF） - Atmel Corporation
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AT91SAM9G46B-CU Datasheet PDF : 1277 Pages
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Table 48-47. USART SPI Timings with 3.3V Peripheral Supply
Symbol
Parameter
Conditions
Min
Max
Unit
SPI0
SPCK Period
–
–
ns
SPI1
Input Data Setup Time
17.2
–
ns
SPI2
SPI3
Input Data Hold Time
Chip Select Active to Serial Clock
0
Master Mode
–
–
ns
3.5
ns
SPI4
Output Data Setup Time
–
0.2
ns
SPI5
Serial Clock to Chip Select Inactive
–
-0.3
ns
SPI6
SPCK falling to MISO
13.8 (1)
16.9 (1)
ns
SPI7
MOSI Setup time before SPCK rises
7.5
–
ns
SPI8
MOSI Hold time after SPCK rises
2.9
–
ns
SPI9
SPCK rising to MISO
4.7 (1)
17.1 (1)
ns
SPI10
MOSI Setup time before SPCK falls
0.4
–
ns
SPI11
MOSI Hold time after SPCK falls
Slave Mode
0
–
ns
SPI12
NPCS0 setup to SPCK rising
10.3
–
ns
SPI13
NPCS0 hold after SPCK falling
2.0
–
ns
SPI14
NPCS0 setup to SPCK falling
10.7
–
ns
SPI15
NPCS0 hold after SPCK rising
2.0
–
ns
SPI16
NPCS0 falling to MISO valid
–
16.0
ns
Notes: 1. For output signals, Min and Max access time must be extracted. The Min access time is the time between the SPCK rising
or falling edge and the signal change. The Max access time is the time between the SPCK rising or falling edge and the
signal stabilization. Figure 48-11 illustrates Min and Max accesses for SPI2. The same applies to SPI5, SPI6, and SPI9.
SAM9G46 Series [DATASHEET]
Atmel-11028G-ATARM-SAM9G46-Datasheet_08-Dec-15
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