PIC32MX230F128L-I/PF 查看數據表（PDF） - Microchip Technology
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PIC32MX230F128L-I/PF
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PIC32MX230F128L-I/PF Datasheet PDF : 382 Pages
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PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY
REGISTER 9-5: DCRCDATA: DMA CRC DATA REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3
31:24
23:16
15:8
7:0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCDATA<31:24>
R/W-0
R/W-0
DCRCDATA<23:16>
R/W-0
R/W-0
DCRCDATA<15:8>
R/W-0
R/W-0
DCRCDATA<7:0>
Bit
26/18/10/2
R/W-0
R/W-0
R/W-0
R/W-0
Bit
25/17/9/1
R/W-0
R/W-0
R/W-0
R/W-0
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 DCRCDATA<31:0>: CRC Data Register bits
Writing to this register will seed the CRC generator. Reading from this register will return the current value of
the CRC. Bits greater than PLEN will return ‘0’ on any read.
When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):
Only the lower 16 bits contain IP header checksum information. The upper 16 bits are always ‘0’. Data written
to this register is converted and read back in 1’s complement form (i.e., current IP header checksum value).
When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):
Bits greater than PLEN will return ‘0’ on any read.
REGISTER 9-6: DCRCXOR: DMA CRCXOR ENABLE REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
31:24
23:16
15:8
7:0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCRCXOR<31:24>
R/W-0
R/W-0
DCRCXOR<23:16>
R/W-0
R/W-0
DCRCXOR<15:8>
R/W-0
R/W-0
DCRCXOR<7:0>
R/W-0
R/W-0
R/W-0
R/W-0
Bit
25/17/9/1
R/W-0
R/W-0
R/W-0
R/W-0
Bit
24/16/8/0
R/W-0
R/W-0
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-0 DCRCXOR<31:0>: CRC XOR Register bits
When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):
This register is unused.
When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):
1 = Enable the XOR input to the Shift register
0 = Disable the XOR input to the Shift register; data is shifted in directly from the previous stage in
the register
DS60001290E-page 94
2014-2017 Microchip Technology Inc.
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