C8051F521A-IM 查看數據表（PDF） - Silicon Laboratories

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C8051F521A-IM

8/4/2 kB ISP Flash MCU Family

Silicon Laboratories 

C8051F52x/F53x

SFR Definition 13.7. P0MAT: Port0 Match

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

11111111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0xD7

Bits7–0: P0MAT[7:0]: Port0 Match Value.

These bits control the value that unmasked P0 Port pins are compared against. A Port

Match event is generated if (P0 & P0MASK) does not equal (P0MAT & P0MASK).

SFR Definition 13.8. P0MASK: Port0 Mask

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0xC7

Bits7–0: P0MASK[7:0]: Port0 Mask Value.

These bits select which Port pins will be compared to the value stored in P0MAT.

0: Corresponding P0.n pin is ignored and cannot cause a Port Match event.

1: Corresponding P0.n pin is compared to the corresponding bit in P0MAT.

Rev. 1.4

131

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