ZPSD413A2-C-15J View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ZPSD413A2-C-15J Datasheet PDF : 123 Pages
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PSD4XX Family
9.0
The PSD4XX
Architecture
(cont.)
Table 3. ZPLD Input Signals
Signal Name
From
PA0 – PA7
Port A inputs or Macrocell PA feedback
PB0 – PB7
Port B inputs or Macrocell PB feedback
PE0 – PE1
Port E inputs (signals ALE, PSEN/BHE)
PGR0 – PGR3
Page Mode Register
A8 – A15, A0, A1
MCU Address Lines
RD/E/DS
MCU bus signal
WR/R_W
MCU bus signal
CLKIN
Input Clock
RESET
Reset input
CSI
CSI input (ORed with power down from PMU)
9.1.1.1 The DPLD
The DPLD is used for internal address decoding generating the following eight chip select
signals:
t ES0 – ES3
EPROM selects, block 0 to block 3
t RS0
SRAM block select
t CSIOP
I/O Decoder chip select
t PSEL0 – PSEL1
Peripheral I/O mode select signals
The I/O Decoder enabled by the CSIOP generates chip selects for on-chip registers or I/O
ports based on address inputs A[7:0].
As shown in Figure 4, the DPLD consists of a large programmable AND ARRAY. There are
a total of 37 inputs and 8 outputs. Each output consists of a single product term. Although
the user can generate select signals from any of the inputs, the select signals are typically
a function of the address and Page Register inputs. The select signals are defined by the
user in the ABEL file (PSDabel).
The address line inputs to the DPLD include A0, A1 and A8 – A15. If more address lines
are needed, the user can bring in the lines through Port A to the DPLD.
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