ZPSD403A2-C-70L View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ZPSD403A2-C-70L

Low Cost Field Programmable Microcontroller Peripherals

STMicroelectronics 

9.0

The PSD4XX

Architecture

(cont.)

PSD4XX Family

9.1.1.2 The GPLD

The structure of the General Purpose PLD consists of a programmable AND ARRAY

and 2 sets of I/O Macrocells. The ARRAY has 37 input signals, same as the DPLD.

From these inputs, “ANDed” functions are generated as product term inputs to the

macrocells. The I/O Macrocell sets are named after the I/O Ports they are linked to,

e.g., the macrocells connected to Port B are named PB Macrocells. The PB macrocells

are registered macrocells with D-type flip-flops, where PA consists of combinatorial

macrocells.

9.1.1.3 TPA Macrocell Structure

Figure 5 shows the PA Macrocell block, which consists of 8 identical combinatorial

macrocells. Each macrocell output can be connected to its own I/O pin on Port A.

There is one user programmable global product term that is output from the GPLD’s

AND ARRAY which is shared by all the macrocells in Port A:

t PA.OE

Enable or tri-state Port A output pins

The circuit of a PA Macrocell is shown in Figure 6. There are 4 product terms from the

GPLD’s AND ARRAY as inputs to the macrocell. Users can select the polarity of the

output, and configure the macrocell to operate as:

t GPLD Input

Use Port A pin as dedicated input

t GPLD Output

Use Port A pin as dedicated output

13

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