PSD403A2-C-70J View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

PSD403A2-C-70J

Low Cost Field Programmable Microcontroller Peripherals

STMicroelectronics 

PSD4XX Family

The PSD4XX

Architecture

(cont.)

Figure 36. Power Management Unit

APD ENABLE

PMMR0 - BIT 2

SLEEP – ENABLE

PMMR1 - BIT 1

ALE POLARITY

PMMR0 - BIT 1

ALE

APD

CLEAR

LOGIC

RESET

APD CLK

CLKIN

MUX

CLR PD

APD

COUNTER

CLK

CSI

APD CLK

PMMR1 - BIT 0

TO OTHER

CIRCUITS

SLEEP

MODE

EPROM

SELECT

Z

SRAM

P SELECT

L I/O

SELECT

D

POWER

DOWN

Figure 36a. Automatic Power Down Unit (APD) Flow Chart

RESET

CSI = "1"

APD DISABLED

NEED YES

APD CLK

NO

SET ALE PD POLARITY

IN PMMRO BIT 1

NEED

SLEEP

MODE

NO

YES

• SET ENABLE APD IN PMMR0 BIT 2

• SET PMMR0 BIT 0

DISABLE CLOCKS

ZPLD ACLK, ZPLD RCLK, TMR ZPLD

ALE IDLE and

15 APD CLOCK

PSD IN POWER DOWN MODE

SET APD CLK IN PMMR1 BIT 0

SET SLEEP MODE IN PMMR1 BIT 1

• SET ENABLE APD IN PMMR0 BIT 2

• SET PMMR0 BIT 0

DISABLE CLOCKS

ZPLD ACLK, ZPLD RCLK, TMR ZPLD

ALE IDLE and

15 APD CLOCK

PSD IN SLEEP MODE

68

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