AD1843
res
Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.
Initial default state after reset: 1000 1000 1000 1000 (8888 hex). Cleared to default and cannot be written
to when: the RESET pin is asserted LO; when the PWRDWN pin is asserted LO; when the PDNO bit in
Control Register Address 0 is set to “1” (all conversions disabled); or when the AAMEN bit (analog input to
analog mix disabled), or the ANAEN bit (analog channels powered down) in Control Register Address 27 is
reset to “0.”
Address 5
Data 15
LX2MM
Data 7
RX2MM
Data 14
res
Data 6
res
Mix Control—Auxiliary 2 to Mixer
Data 13
Data 12
Data 11
Data 10
res
LX2M4
LX2M3
LX2M2
Data 5
Data 4
Data 3
Data 2
res
RX2M4
RX2M3
RX2M2
Data 9
LX2M1
Data 1
RX2M1
Data 8
LX2M0
Data 0
RX2M0
LX2MM
LX2M4:0
RX2MM
RX2M4:0
res
Left Auxiliary 2 Mix Mute
0 = Mix Enabled
1 = Mix Muted
Left Auxiliary 2 Mix Gain/Attenuation Select. Least significant bit represents –1.5 dB. Referred to
2.0 V p-p DAC1 output level.
00000 = +12.0 dB Gain
01000 = 0.0 dB
11111 = –34.5 dB Attenuation
Right Auxiliary 2 Mix Mute
0 = Mix Enabled
1 = Mix Muted
Right Auxiliary 2 Mix Gain/Attenuation Select. Least significant bit represents –1.5 dB. Referred to
2.0 V p-p DAC1 output level.
00000 = +12.0 dB Gain
01000 = 0.0 dB
11111 = –34.5 dB Attenuation
Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.
Initial default state after reset: 1000 1000 1000 1000 (8888 hex). Cleared to default and cannot be written to when:
the RESET pin is asserted LO; when the PWRDWN pin is asserted LO; when the PDNO bit in Control Register Ad-
dress 0 is set to “1” (all conversions disabled); or when the AAMEN bit (analog input to analog mix disabled), or the
ANAEN bit (analog channels powered down) in Control Register Address 27 is reset to “0.”
Address 6
Data 15
LX3MM
Data 7
RX3MM
Data 14
res
Data 6
res
Mix Control—Auxiliary 3 to Mixer
Data 13
Data 12
Data 11
Data 10
res
LX3M4
LX3M3
LX3M2
Data 5
Data 4
Data 3
Data 2
res
RX3M4
RX3M3
RX3M2
Data 9
LX3M1
Data 1
RX3M1
Data 8
LX3M0
Data 0
RX3M0
LX3MM
LX3M4:0
Left Auxiliary 3 Mix Mute
0 = Mix Enabled
1 = Mix Muted
Left Auxiliary 3 Mix Gain/Attenuation Select. Least significant bit represents –1.5 dB. Referred to
2.0 V p-p DAC1 output level.
00000 = +12.0 dB Gain
01000 = 0.0 dB
11111 = –34.5 dB Attenuation
REV. 0
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