(13) Port P56
Direction register
Data bus
Port latch
TOUT output control bit
Timer output
MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Pul-up control
(14) Port P6
Direction register
Data bus
Port latch
Pull-up control
A-D conversion input
Analog input pin selection bit
(15) Port P70
Port XC switch bit + Pull-up control
Port XC switch bit
Direction register
Data bus
Port latch
(16) Port P71
Port XC switch bit + Pull-up control
Port XC switch bit
Direction register
Data bus
Port latch
(17) COM0–COM3
VL3
VL2
VL1
Oscillation circuit
Port P71
Port XC switch bit
Sub-clock generating circuit input
(18) SEG0–SEG11
VL2/VL3
The gate input signal of each transistor is
controlled by the LCD duty ratio and the
bias value.
VL1/VSS
The voltage applied to the sources of
P-channel and N-channel transistors
is the controlled voltage by the bias
value.
Fig. 17 Port block diagram (3)
21